Zobrazeno 1 - 7
of 7
pro vyhledávání: '"David Guerrero-Martos"'
Autor:
German Cano-Quiveu, Paulino Ruiz-De-Clavijo-Vazquez, Manuel J. Bellido-Diaz, David Guerrero-Martos, Julian Viejo-Cortes, Jorge Juan-Chico
Publikováno v:
IEEE Access, Vol 9, Pp 161383-161394 (2021)
This paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the proposed framework is based on the development of a high level software model, an HDL description of the IPCore and the verificati
Externí odkaz:
https://doaj.org/article/35005663a3524faf91c36de35f85f9d7
Autor:
David Guerrero Martos, Alejandro Millán Calderón, Jorge Juan Chico, Julian Viejo Cortés, Manuel J. Bellido Díaz, Paulino Ruiz-de-Clavijo Vazquez, Enrique Ostúa Arangüena
Publikováno v:
EURASIP Journal on Advances in Signal Processing, Vol 2020, Iss 1, Pp 1-21 (2020)
Abstract The computation of the sine and cosine functions is required in devices ranging from application-specific signal processors to general purpose floating-point units. Even in the latter case, the required functionality can be reduced to comput
Externí odkaz:
https://doaj.org/article/0007e0226ab44d3aa39a48017128c759
Autor:
German Cano-Quiveu, Paulino Ruiz-de-clavijo-Vazquez, Manuel J. Bellido, Jorge Juan-Chico, Julian Viejo-Cortes, David Guerrero-Martos, Enrique Ostua-Aranguena
Publikováno v:
Electronics; Volume 10; Issue 23; Pages: 3036
Electronics, Vol 10, Iss 3036, p 3036 (2021)
Electronics, Vol 10, Iss 3036, p 3036 (2021)
The Internet of Things (IoT) security is one of the most important issues developers have to face. Data tampering must be prevented in IoT devices and some or all of the confidentiality, integrity, and authenticity of sensible data files must be assu
Autor:
Manuel Jesús Bellido Díaz, Julián Viejo Cortés, Jorge Juan Chico, Enrique Ostúa Arangüena, David Guerrero Martos, Alejandro Millán Calderón, Paulino Ruiz-de-Clavijo Vazquez
Publikováno v:
EURASIP Journal on Advances in Signal Processing, Vol 2020, Iss 1, Pp 1-21 (2020)
The computation of the sine and cosine functions is required in devices ranging from application-specific signal processors to general purpose floating-point units. Even in the latter case, the required functionality can be reduced to computing the s
Publikováno v:
Logic-Timing Simulation and the Degradation Delay Model
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e51f2902ad815027a017ae8dc15b73ea
https://doi.org/10.1142/9781860947360_0002
https://doi.org/10.1142/9781860947360_0002
Publikováno v:
Logic-Timing Simulation and the Degradation Delay Model
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b9e729f6e633c799c886f2aeca5fa669
https://doi.org/10.1142/9781860947360_0003
https://doi.org/10.1142/9781860947360_0003
Autor:
J. Juan-Chico, E. Ostua, David Guerrero Martos, Alejandro Millán Calderón, Paulino Ruiz de Clavijo, Manuel J. Díaz, J. Viejo
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540290131
PATMOS
PATMOS
In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its internal nodes allowing to consid
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ed64555f30f7142b663bb52b63ee9080
https://doi.org/10.1007/11556930_35
https://doi.org/10.1007/11556930_35