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of 5
pro vyhledávání: '"David Greenhill"'
Autor:
Stuart David Greenhill, Sophie Elizabeth Lyn Chamberlain, Alex Lench, Peter Vernon Massey, Kathryn Heather Yuill, Gavin Lawrence Woodhall, Roland Spencer Gwynne Jones
Publikováno v:
PLoS ONE, Vol 9, Iss 1, p e85125 (2014)
The entorhinal cortex (EC) controls hippocampal input and output, playing major roles in memory and spatial navigation. Different layers of the EC subserve different functions and a number of studies have compared properties of neurones across layers
Externí odkaz:
https://doaj.org/article/09c49e9069ef418d9a565cf92ffe3c2e
Autor:
Ashkan Hashemi, David Greenhill, Hyo-Soon Kang, Xiaoping Liu, Chandrasekar Karthik, Guang Chen, Changwook Yoon, Wendemagegnehu T. Beyene
Publikováno v:
2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
The study of the optimal data rates of high-speed channels supported by typical high-performance FPGA chips is presented. First, the representative channels are grouped into distinct categories that have drastically dissimilar characteristics. Conseq
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::411c487a87860366ddd8893c9d082982
https://doi.org/10.1109/epeps.2018.8534244
https://doi.org/10.1109/epeps.2018.8534244
Publikováno v:
2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
Silicon bridge is a promising solution that provides communication paths among multiple SoCs in a single package. It also provides a low-impedance path for the power delivery between two or more SoCs. However, a congested dense signal routing inside
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::59405c39ff39de650ebad013413e552e
https://doi.org/10.1109/epeps.2018.8534288
https://doi.org/10.1109/epeps.2018.8534288
Autor:
Wei-Yee Koay, Ty Garibay, Han Wooi Lim, Ron Ho, Andy Tong, Darren Faulkner, David Lewis, David Greenhill, Dana How, Herman Schmit, Peter McElheny, George Chen, Gopal Iyer, Duwel Keith, Jeffrey Erik Schulz, Atsatt Sean R, Hee Kong Phoon, Kok Hong Chan
Publikováno v:
ISSCC
A Field Programmable Gate Array (FPGA) family was designed to match a programmable fabric die built in 14nm process technology with 28Gb/s transceiver dice. The 2.5D packaging (Fig. 3.3.1) uses embedded interconnect bridges (EMIB) [1]. 20nm transceiv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76ed4121fcf1fd8c4e17fa2811f98989
https://doi.org/10.1109/isscc.2017.7870257
https://doi.org/10.1109/isscc.2017.7870257
Conference
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