Zobrazeno 1 - 4
of 4
pro vyhledávání: '"David A. Hrusecky"'
Autor:
Joachim Gerhard Clabes, Joshua Friedrich, J. Kahle, William J. Starke, Daniel M. Dreps, Victor Zyuban, James D. Warnock, Robert Alan Cargnoni, S. Weitzel, Scott A. Taylor, Phillip G. Williams, Jose Angel Paredes, Dieter Wendel, J. Pille, Gaurav Mittal, Saiful Islam, G Smith, J. A. Van Norstrand, Balaram Sinharoy, Phillip J. Restle, David A. Hrusecky, Sam Gat-Shang Chu, Ronald Nick Kalla, Jentje Leenstra
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:145-161
This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 56
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9efa8df1eb9cc07c1be4577681cd9147
https://doi.org/10.1109/jssc.2010.2080611
https://doi.org/10.1109/jssc.2010.2080611
Autor:
Michael Kroener, J. A. Van Norstrand, Thompto Brian W, Hung Qui Le, José E. Moreira, David A. Hrusecky, M. J. Genden, Dung Quoc Nguyen
Publikováno v:
IBM Journal of Research and Development. 62:2:1-2:12
The IBM POWER9 processor is the latest Reduced Instruction Set Computer microprocessor from IBM. POWER9 employs a new modular core microarchitecture to counter the technology trend of decreasing frequency and increasing power density from generation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c1a2dc9d7482d76a94e0629b17253894
https://doi.org/10.1147/jrd.2018.2854039
https://doi.org/10.1147/jrd.2018.2854039
Autor:
Otto Wagner, Juergen Pille, Jose Angel Paredes, Stefan Buettner, M. Canada, Thomas Froehnel, Rolf Sautter, David Scott Ray, Otto Torreiter, Martin Eckert, David A. Hrusecky, Dieter Wendel, Wolfgang Penth
Publikováno v:
ISSCC
Increasing demand for parallelism due to out-of-order and multi-threading computation requires fast and dense arrays with multi-port capabilities. The load-store-unit (LSU) of the POWER7™ microprocessor core has a 32kB L1 data cache composed of fou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f48529f0c91954422deea2ba23dd3fdd
https://doi.org/10.1109/isscc.2010.5433849
https://doi.org/10.1109/isscc.2010.5433849
Autor:
James Wilson Bishop, Kimberly Marie Fernsler, Hung Qui Le, Markus Kaltenbach, Dung Quoc Nguyen, David Stephen Levitan, Brian R. Konigsburg, Richard J. Eickemeyer, Mary D. Brown, J. A. Van Norstrand, S. Tung, Balaram Sinharoy, José E. Moreira, Michael K. Gschwind, Tejas Karkhanis, David A. Hrusecky, Maarten J. Boersma, Jentje Leenstra, Michael Kroener, Kenneth L. Ward
Publikováno v:
IBM Journal of Research and Development. 59:2:1-2:21
The POWER8™ processor is the latest RISC (Reduced Instruction Set Computer) microprocessor from IBM. It is fabricated using the company's 22-nm Silicon on Insulator (SOI) technology with 15 layers of metal, and it has been designed to significantly
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d54d876ab12422f9a7e53262eb4c533b
https://doi.org/10.1147/jrd.2014.2376112
https://doi.org/10.1147/jrd.2014.2376112