Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Datapath circuits"'
Autor:
Piccoli, Michele, Zoni, Davide, Fornaciari, William, Massari, Giueppe, Cococcioni, Marco, Rossi, Federico, Saponara, Sergio, Ruffaldi, Emanuele
Since its introduction in 2017, the Posit™ format for representing real numbers has attracted a lot of interest, as an alternative to IEEE 754 floating point representation. Several hardware implementations of arithmetic operations between posit nu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7515cfeaf758e24388846e5c4ea9f02a
Autor:
Muyu Yang, Erdal Oruklu
Publikováno v:
MWSCAS
The Gate-All-Around (GAA) FET device structure is expected to become the next widely used evolution of FET architecture in the near future. In this paper, full-adder datapath circuits using Lateral GAA FETs (LGAA FETs) based on BSIMCMG model are anal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc87791b72538e68f399534933d4d5aa
https://doi.org/10.1109/mwscas.2018.8623926
https://doi.org/10.1109/mwscas.2018.8623926
Autor:
Har Narayan Upadhyay, V. Elamaran
Publikováno v:
Asian Journal of Scientific Research. 8:478-489
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::21c40dd29791cbd28278f171904bd4ee
https://doi.org/10.3923/ajsr.2015.478.489
https://doi.org/10.3923/ajsr.2015.478.489
Publikováno v:
ISLPED
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
The need for power-efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a re-tailoring for the mobile market that they are entering now
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e20c612fe0358888da1142d1f9dc6f93
https://doi.org/10.1145/2934583.2934587
https://doi.org/10.1145/2934583.2934587
Autor:
Erdal Oruklu, Yu Yuan
Publikováno v:
EIT
Due to its reduced leakage and suppressed short channel effects, FinFET has been adopted by semiconductor industry to replace conventional bulk CMOS on most advanced process nodes. In this paper, performance of Predictive Technology Model (PTM) and B
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7580a0e6c61a142007140b9e78f8e768
https://doi.org/10.1109/eit.2016.7535313
https://doi.org/10.1109/eit.2016.7535313
Publikováno v:
High Performance Integer Arithmetic Circuit Design on FPGA ISBN: 9788132225195
This chapter discusses some common arithmetic datapath circuits which can significantly contribute to the critical path delay, either due to their long, cascading path delay, or undesirable inference of logic elements and their irregular placement on
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::904220b7fd31313688fae482af83e063
https://doi.org/10.1007/978-81-322-2520-1_4
https://doi.org/10.1007/978-81-322-2520-1_4
Autor:
Bijan Alizadeh, Masahiro Fujita
Publikováno v:
HLDVT
This paper presents an automatic test pattern generation (ATPG) technique applicable to register transfer level (RTL) datapath circuits which are usually very hard-to-test due to the presence of complex loop structures. Although to achieve high fault
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0cd57643c6030f117031ceb3f7262a20
https://doi.org/10.1109/hldvt.2012.6418244
https://doi.org/10.1109/hldvt.2012.6418244
Autor:
Jonathan Rose, Andy Ye
Publikováno v:
FPGA
As the logic capacity of Field-Programmable Gate Arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::996b1717f64095aca426ec7fdd821494
https://doi.org/10.1145/1046192.1046194
https://doi.org/10.1145/1046192.1046194
Autor:
Jung-Lin Yang, Erik Brunvand
Publikováno v:
2005 International Symposium on Intelligent Signal Processing and Communication Systems.
We present a technique for generating robust self-timed completion signals for general dynamic datapath circuits. The wrapper circuit is based on our previous domino semi-bundled delay (SBD) circuits, but uses DCVSL circuits in the wrapper for higher
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::46129a6e1f852505f3268134f2fbe0de
https://doi.org/10.1109/ispacs.2005.1595441
https://doi.org/10.1109/ispacs.2005.1595441
Publikováno v:
VTS
Scopus-Elsevier
Scopus-Elsevier
We present a low-cost on-line test methodology for RTL controller-datapath pairs, based on the notion of path invariance. The fundamental observation supporting the proposed methodology is that the transparency behavior inherent in RTL components ren
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e0bf57accc4651d15946462d60a54f3d
https://doi.org/10.1109/vtest.2000.843879
https://doi.org/10.1109/vtest.2000.843879