Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Darius Tanksalvala"'
Publikováno v:
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
A Reduced Instruction Set Computer using direct hardware instruction decode and 3-stage pipelined execution will be described. At an operating frequency of 30MHz, a 120Mbytes/s transfer rate on an external cache/coprocessor interface is achieved. NMO
Autor:
Michael A Buckley, Craig A. Gleason, D. Hollenbeck, Richard J. Luebs, K. Erskine, Joel D. Lamb, B. Long, J. Wheeler, S. McMullen, J. Yetter, C. Kohlhardt, H. Hill, Daniel L Halperin, Jonathan P Lotz, Robert J. Horning, Patrick Knebel, R. Novak, Darius Tanksalvala, H. Tran, L. Sigel, C. Simpson, Doug Quarnstrom, Donald Kipp, John R. Spencer, S. Chapin, Eric Delano, Duncan Weir, E. Rashid, Thomas R. Hotchkiss, M. Forsyth, T. Gaddis
Publikováno v:
1990 37th IEEE International Conference on Solid-State Circuits.
A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both comme
Publikováno v:
IEEE Journal of Solid-State Circuits. 22:768-775
A 32-b single-chip VLSI CPU which implements the entire 140 instructions of the Hewlett-Packard precision architecture (HPPA) using direct hardwired decoding and execution is described. A sustained pipeline performance of 10.8 million instructions pe
Conference
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