Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Dario Suarez-Gracia"'
Publikováno v:
IEEE Access, Vol 8, Pp 173276-173288 (2020)
The ever-increasing parallelism demand of General-Purpose Graphics Processing Unit (GPGPU) applications pushes toward larger and more energy-hungry register files in successive GPU generations. Reducing the supply voltage beyond its safe limit is an
Externí odkaz:
https://doaj.org/article/415587979e5d45c9a0825edd34fb90a6
Publikováno v:
2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS).
Autor:
Jesús Alastruey-Benedé, Víctor Viñals Yúfera, Teresa Monreal Arnal, Alexandra Ferrerón, Pablo Enrique Ibáñez Marín, Dario Suarez Gracia
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Zaguán. Repositorio Digital de la Universidad de Zaragoza
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Zaguán. Repositorio Digital de la Universidad de Zaragoza
Voltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent with a hard fault. Block
Publikováno v:
Zaguán. Repositorio Digital de la Universidad de Zaragoza
instname
instname
High performance computing (HPC) demands huge memory bandwidth and computing resources to achieve maximum performance and energy efficiency. FPGAs can provide both, and with the help of High Level Synthesis, those HPC applications can be easily writt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8b57faa5e248f5adfd5edffc4315effe
http://zaguan.unizar.es/record/109408
http://zaguan.unizar.es/record/109408
Publikováno v:
Jornada de Jóvenes Investigadores del I3A. 8
Mejorar el rendimiento en sistemas de cómputo ha impulsado el uso de aceleradores como FPGAs. Este trabajo presenta 2 propuestas que aúnan su programabilidad y rendimiento utilizando síntesis de alto nivel, HLS, con FPGAs: 1) A través del anális
Publikováno v:
FCCM
HLS tools simplify programming for FPGAs, but generating highly tuned code still remains a challenge because CPU and GPU optimization techniques are not always directly applicable to FPGA. Besides, bitstream generation takes a long time, preventing a
Autor:
Adolfo Muñoz, Enrique F. Torres, Ruben Gran Tejero, Ana C. Murillo, Jesús Alastruey-Benedé, Javier Resano, Pablo Ibáñez, Eduardo Montijano, José Luis Briz, Joaquín Ezpeleta, María Villarroya-Gaudó, Alejandro Valero, Luis M. Ramos, Pedro Álvarez, Dario Suarez Gracia, Agustín Navarro-Torres, Víctor Viñals
Publikováno v:
WCAE@ISCA
For students of any Computer Engineering program, attaining an integrated vision of the different abstraction levels is paramount to fully understand and exploit a computer system, especially when tough topics such as parallelism, concurrency, consis
Autor:
Wenjia Ruan, Calin Cascaval, Dario Suarez Gracia, Aravind Natarajan, Mario Badr, Tushar Kumar
Publikováno v:
Languages and Compilers for Parallel Computing ISBN: 9783030352240
LCPC
LCPC
Data management across address spaces in heterogeneous platforms represents a significant performance bottleneck and energy cost for applications, particularly on mobile System-on-Chip (SoC). We propose a light-weight middleware layer to regulate con
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1c75ef5a04c723ccd99487545f401016
https://doi.org/10.1007/978-3-030-35225-7_11
https://doi.org/10.1007/978-3-030-35225-7_11
Autor:
Maria Angélica Dávila Guzmán, José Luis Bosque, Ruben Gran Tejero, María Villarroya-Gaudó, Raúl Nozal, Dario Suarez Gracia
Publikováno v:
Zaguán. Repositorio Digital de la Universidad de Zaragoza
Consejo Superior de Investigaciones Científicas (CSIC)
Consejo Superior de Investigaciones Científicas (CSIC)
Heterogeneous systems are the core architecture of most of the high-performance computing nodes, due to their excellent performance and energy efficiency. However, a key challenge that remains is programmability, specifically, releasing the programme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8d4fd16509a96f7509eda959ad1feb0b
http://zaguan.unizar.es/record/88471
http://zaguan.unizar.es/record/88471
Publikováno v:
HPCS
Nowadays, most commodity heterogeneous systems consist in either a CPU+GPU or CPU+FPGA. An attractive alternative consists in merging both in a new class of heterogeneous system: CPU+GPU+FPGA in order to combine the advantages of all of them into a s