Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Daniel Yingling"'
Autor:
Hoan Huu Nguyen, Anthony Polomik, Amer Cassier, Francois Ibrahim Atallah, Jihoon Jeong, Arijit Raychowdhury, Mahesh Harinath, Samantak Gangopadhyay, Nathaniel Reeves, Keith Bowman, Daniel Yingling, Brad Appel
Publikováno v:
IEEE Solid-State Circuits Letters. 2:297-300
A 7-nm leakage-current-supply (LCS) circuit monitors leakage across process and temperature variations and controls PFET block-head switches (BHSs) to supply the slow-changing leakage current while a high-bandwidth analog low-dropout (LDO) voltage re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d65068db4af80a8031bf0978c9259b21
https://doi.org/10.1109/lssc.2019.2947239
https://doi.org/10.1109/lssc.2019.2947239
Publikováno v:
IEEE Solid-State Circuits Letters. 1:225-228
A 7-nm register file (RF) with a 16-transistor (16T) 3-read and 3-write (3R3W) bitcell double pump or time multiplexes the read and write access ports twice per clock cycle to achieve 6-read and 6-write (6R6W) operations per cycle for high-bandwidth
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::045daff343e7584933e5de2715898d5f
https://doi.org/10.1109/lssc.2019.2911885
https://doi.org/10.1109/lssc.2019.2911885
Autor:
Rahim Masoudi, Dipak Mandel, Nis Mohamad, Amir Hossein Ansari, Hadi B. Amat, Daniel Yingling, Shahab D. Mohaghegh, Ali Sabzabadi
Publikováno v:
Day 4 Thu, October 29, 2020.
Using commercial numerical reservoir simulators to build a full field reservoir model and simultaneously history match multiple dynamic variables for a highly complex, offshore mature field in Malaysia, had proven to be challenging, manpower intensiv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1871f6f199b801372edc83102ecdbaea
https://doi.org/10.2118/201693-ms
https://doi.org/10.2118/201693-ms
Autor:
Daniel Yingling, Anthony Polomik, Yu Sun, Thomas Moore, Hoan Nguyen, Joshua Morelli, Brad Appel, Mahesh Harinath, Francois Ibrahim Atallah, Nathaniel Reeves, Arijit Raychowdhury, Amer Cassier, Keith Bowman, Jihoon Jeong
Publikováno v:
ISSCC
Conventional processors regulate the supply voltage (V DD ) and clock frequency (F CLK ) in two separate and independent control loops. A buck converter, switched-capacitor, or low-dropout (LDO) voltage regulator are example control loops for regulat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c9fc8593979b3374ed6fbd792140c8f3
https://doi.org/10.1109/isscc.2019.8662381
https://doi.org/10.1109/isscc.2019.8662381
Autor:
Jihoon Jeong, Francois Ibrahim Atallah, Keith Bowman, J. Todd Bridges, Daniel Yingling, Brad Appel, Sarthak Raina, David W. Hansquine, Hoan Huu Nguyen, Yesh Kolla
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:8-17
A 16 nm all-digital auto-calibrating adaptive clock distribution (ACD) enhances processor core performance and energy efficiency by mitigating the adverse effects of high-frequency supply voltage $({\rm V}_{\rm DD})$ droops. The ACD integrates a tuna
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4a5bb073b6ab4cb4e1d338ceb6cf847
https://doi.org/10.1109/jssc.2015.2473655
https://doi.org/10.1109/jssc.2015.2473655
Autor:
Marc Jansen, Keith Bowman, Hoan Nguyen, Francois Ibrahim Atallah, Brad Appel, Harsha Akkaraju, Anthony Polomik, Jihoon Jeong, Nadkarni Rahul Krishnakumar, Daniel Yingling
Publikováno v:
VLSI Circuits
A 7nm register file (RF) based on a 3-read and 3-write (3R3W) bitcell operates the access ports twice per clock cycle to achieve 6R6W operations per cycle for high-bandwidth (BW) on-die memory in machine learning (ML) processors. Silicon test-chip me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fb338b079895110770bdb09ebb022440
https://doi.org/10.1109/vlsic.2018.8502393
https://doi.org/10.1109/vlsic.2018.8502393
Autor:
Hoan Nguyen, Keith Bowman, Jihoon Jeong, Daniel Yingling, Yesh Kolla, Francois Ibrahim Atallah, Brad Appel, Todd Bridges, David W. Hansquine, Sarthak Raina
Publikováno v:
ISSCC
System-on-chip (SoC) processor cores experience high-frequency supply voltage (V DD ) droops when the current in the power delivery network abruptly changes in response to workload variations, thus degrading performance and energy efficiency. Previou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e101fc6371f0e48adf1671fbb098f34
https://doi.org/10.1109/isscc.2015.7062971
https://doi.org/10.1109/isscc.2015.7062971