Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Daniel W. Dobberpuhl"'
Autor:
J. Grodstein, Insung Kim, Daniel C. Murray, D. Bertucci, J. Burnette, A.J. Baum, R. Stepanian, V.R. van Kaenel, R. Wen, D. Souydalay, A. Spink, Amy K. Silveria, M. Pearce, A. Varadharajan, K. Broch, T. Broch, S. Santhanam, Kwong-Tak Chui, E. Chang, Daniel W. Dobberpuhl, M. Braganza, P. Donahue
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1829-1839
This paper describes the 300-MHz StrongARM 1500 microprocessor, which is capable of more than two billion 16-b operations per second. Starting with the original StrongARM 110 design, an attached media processor (AMP) has been integrated along with a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f8110a9bbe9af8e5e70ee8733f9d7675
https://doi.org/10.1109/4.726584
https://doi.org/10.1109/4.726584
Autor:
R. Witek, S.C. Thierauf, M. Pearce, P. Donahue, K. Snyder, Daniel C. Murray, G. Hoeppner, Elizabeth M. Cooper, P. Lin, Thomas H. Lee, L. Madden, S. Santhanam, J. Eno, J. Montanaro, A.J. Black, A. Farell, Daniel W. Dobberpuhl, R. Stephany, K. Anne, D. Kruckemyer
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:1703-1714
This paper describes a 160 MHz 500 mW 32 b StrongARM(R) microprocessor designed for low-power, low-cost applications. The chip implements the ARM(R) V4 instruction set and is bus compatible with earlier implementations. The pin interface runs at 3.3
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9389192c87c82606779a5e2928ebfdcd
https://doi.org/10.1109/jssc.1996.542315
https://doi.org/10.1109/jssc.1996.542315
Autor:
V. Rajagopalan, D.E. Dever, R. Witek, D.R. Meyer, S. Santhanam, S.M. Britton, R. Allmon, Donald A. Priore, D. Bertucci, L. Chao, B. Gieseke, M. Ladd, Edward J. McLellan, K. Kuchler, G. Hoeppner, L. Madden, Soha Hassoun, R.A. Conrad, R. Anglin, Daniel W. Dobberpuhl, S. Samudrala, J. Montanaro, B.M. Leary
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:1555-1567
A RISC (reduced-instruction-set computer)-style microprocessor operating up to 200 MHz, implements a 64-b architecture that provides huge linear address space without bottlenecks that would impede highly concurrent implementations. Fully pipelined an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d18d3235054e804b1e9662dda9eac217
https://doi.org/10.1109/4.165336
https://doi.org/10.1109/4.165336
Autor:
J. Kowaleski, R. Stamm, R. Witek, M. Ladd, R. Devlin, S. Morris, G. Hoeppner, H. Tumblin, J. Montanaro, R. Heye, Daniel W. Dobberpuhl, B. Gieseke, R.A. Conrad
Publikováno v:
IEEE International Solid-State Circuits Conference.
An RISC (reduced-instruction-set-computer) microprocessor is described that, subject to data dependencies, can issue one 32-b instruction every 20-ns cycle to achieve peak performance of 50 MIPS (million instructions per second) for worst-case proces
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a8a0e2da153fbc1d2d66831fe4ce1e1
https://doi.org/10.1109/isscc.1989.48185
https://doi.org/10.1109/isscc.1989.48185
Autor:
L. O'Donnell, V. Sundaresan, Brian J. Campbell, Tuan Do, G. Yee, R. Blake, Donald A. Priore, N. Bunger, Daniel C. Murray, E. Supnet, D. Kidd, Ingino Joseph M, D. Rodriguez, M. Pearce, G. Yiu, Sribalan Santhanam, Jong Lee, M. Carlson, K. Anne, V. von Kaenel, J. Cheng, C. Vo, Robert Rogenmoser, S. Nishimoto, R. Wen, Dongwook Suh, Zongjian Chen, David A. Kruckemyer, M. Panich, Daniel W. Dobberpuhl, M. Oykher, R. Allmon
Publikováno v:
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3ecd1e71f24d74a85e5bf3a4ddc378b
https://doi.org/10.1109/vlsic.2001.934209
https://doi.org/10.1109/vlsic.2001.934209
Autor:
Daniel W. Dobberpuhl
Publikováno v:
Third Caltech Conference on Very Large Scale Integration ISBN: 9783540123699
The Mead-Conway approach to VLSI provides a path for non-specialists to enter the world of VLSI design. The approach condenses most of the more esoteric aspects of circuits and devices into simpler rules of thumb, which, when applied in the context o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bfd03927193cb458a085a956d81c4b32
https://doi.org/10.1007/978-3-642-95432-0_4
https://doi.org/10.1007/978-3-642-95432-0_4
Autor:
M. Miller, M. Doherty, R. Witek, E. Dornekamp, D. Grondalski, K. Henry, B. Supnik, B. Grondalski, J. Beck, Daniel W. Dobberpuhl, S.C. Thierauf
Publikováno v:
1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
The development of a 140,000 transistor 32b single chip microprocessor, implementing a superminicomputer's 304 instructions will be described. The chip is 8.5 × 8.0mm and dissipates 3W.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c3d4ea49aab673821011b557e66ae4b9
https://doi.org/10.1109/isscc.1984.1156652
https://doi.org/10.1109/isscc.1984.1156652
Akademický článek
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Conference
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