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Autor:
Han Lokker, Michiel van Duuren, Yi Ning Chen, Jochen Garbe, Alessandro Baiano, Daniel Tajari Mofrad, D. Dormans, Jouke Verbree, Kitty van Dijk, Yu Chen, Hans van Zwol, Robert Beurze, R. Verhaar, Bob Schippers, Jed Chiang, Erik van der Vegt
Publikováno v:
2015 IEEE International Memory Workshop (IMW).
2-transistor (2T) cell technology used for embedded non-volatile memory (eNVM) has been scaled down to 40nm node. To enable aggressive cell scaling, the array architecture is modified compared to previous generations and the channel length of cell is