Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Daniel R. Knebel"'
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 54:586-590
Most existing power gating structures provide only one power-saving mode. We propose a novel power gating structure that supports both a cutoff mode and an intermediate power-saving and data-retaining mode. Experiments with test structures fabricated
Autor:
Melanie J. Sherony, M. Rivier, P. O'Neil, Yue Tan, Asit Kumar Ray, Mohamed Talbi, Lawrence F. Wagner, N. E. Lustig, Kun Wu, Jean-Olivier Plouchart, Daniel R. Knebel, David M. Friend, Keith A. Jenkins, Shreesh Narasimha, Noah Zamdmer, Jae-Joon Kim, Seong-Dong Kim, M. Rohn, J. Strom, Nghia Van Phan, Stephen V. Kosonocky
Publikováno v:
IBM Journal of Research and Development. 47:611-629
Systems-on-chips (SoCs) that combine digital and high-speed communication circuits present new opportunities for power-saving designs. This results from both the large number of system specifications that can be traded off to minimize overall power a
Autor:
Victor Zyuban, Ken K. Chin, W. Hwang, Suhwan Kim, Kevin Wilson Warren, George D. Gristede, Daniel R. Knebel, M. B. Ketchen, Azeez Bhavnagarwala, Stephen V. Kosonocky, A.-M. Haen
Publikováno v:
IBM Journal of Research and Development. 47:283-298
As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a g
Autor:
William V. Huott, Steven E. Steen, Jeffrey A. Kash, James C. Tsang, Stas Polonsky, M.K. Mc Manus, Daniel R. Knebel
Publikováno v:
Microelectronics Reliability. 40:1353-1358
Normal operation of complementary metal-oxide semiconductor (CMOS) devices entails the emission of picosecond pulses of light, which can be used to diagnose circuit problems. The pulses that are observed from submicron sized field effect transistors
Publikováno v:
IBM Journal of Research and Development. 43:899-914
This paper describes the strategies and techniques used to diagnose failures in the IBM 600-MHz S/390® G5 (Generation 5) CMOS microprocessor and the associated cache chips. The complexity, density, cycle time, and technology issues related to the ha
Publikováno v:
ISLPED
A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and
Autor:
David F. Heidel, Kevin Stawiasz, Daniel R. Knebel, Suhwan Kim, M. Immediato, Stephen V. Kosonocky
Publikováno v:
ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).
A multiple power domain strategy in which each power domain has an independent power gating structure is an effective means for reducing leakage power consumption in a system-on-a-chip. During an individual power gating structure power-mode transitio
Publikováno v:
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).
New SRAM circuit techniques implemented in a standard 0.13 /spl mu/m bulk Si CMOS process are reported in this work that (i) enable pico-joule energy dissipation per accessed bit at 1 GHz, (ii) lower total leakage power by over 80% from all unaccesse
Autor:
Pia Naoko Sanda, H.F. Casal, E. Seewann, Daniel R. Knebel, Jeffrey A. Kash, M. Papermaster, James C. Tsang
Publikováno v:
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
Picosecond imaging circuit analysis (PICA) is shown to be a valuable means for measuring internal timing of microprocessors operating at speed. In this paper, PICA is applied to the analysis of delays and skew of the IBM POWER3 64b microprocessor clo
Autor:
Daniel R. Knebel, Moyra K. McManus, J. Lee, Peilin Song, Mary P. Kusko, Franco Motika, Richard F. Rizzolo
Publikováno v:
ITC
This paper describes strategies and techniques used to diagnose failures in the IBM 600 MHz G5 (Generation 5) CMOS microprocessor and associated cache chips. Time-to-market pressure demands quick diagnostic turnaround time while the complexity, densi