Zobrazeno 1 - 10
of 58
pro vyhledávání: '"Daniel M. Dreps"'
Autor:
Daniel M. Dreps, Mahesh Bohra, Wiren D. Becker, Dierk Kaller, Jose A. Hejase, Xiaomin Duan, Xianbo Yang, Yanyan Zhang, Junyan Tang
Publikováno v:
2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3bfd9d457f50e41f38c0006270e2b10c
https://doi.org/10.1109/epeps51341.2021.9609151
https://doi.org/10.1109/epeps51341.2021.9609151
Autor:
Daniel M. Dreps, Mahesh Bohra, Lloyd A. Walls, Wiren D. Becker, Xianbo Yang, Yanyan Zhang, Junyan Tang
Publikováno v:
2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::23b533814d39bddcb7ab49a80b1f13e9
https://doi.org/10.1109/epeps51341.2021.9609136
https://doi.org/10.1109/epeps51341.2021.9609136
Autor:
Wiren D. Becker, Daniel M. Dreps, Pavel Roy Paladhi, Brian Samuel Beaman, Yanyan Zhang, Jose A. Hejase, Junyan Tang, Daniel Rodriguez, Sungjun Chun
Publikováno v:
2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
A comprehensive signal integrity model to hardware correlation study on an improved, 44 Gb/s capable, hybrid land grid array (HLGA) socket connector design is presented. The connector only design SI performance is shown through 3D electromagnetic (EM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18caab087dcff7de491f99354276ba92
https://doi.org/10.1109/epeps48591.2020.9231393
https://doi.org/10.1109/epeps48591.2020.9231393
Publikováno v:
2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
The characterization of the signal integrity (SI) performance of differential high-speed channels that have an imbalance due to mismatched via stub length is investigated. The impact of the asymmetric stubs are characterized with regards to impedance
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eabcb5c1ec7e3ba9a4a57daab1c8a909
https://doi.org/10.1109/epeps48591.2020.9231479
https://doi.org/10.1109/epeps48591.2020.9231479
Autor:
Thomas Morf, Chris Steffen, Daniel M. Dreps, Nathan Blanchard, Marcel Kossel, Pier Andrea Francese, Michael B. Spear, Glen A. Wiedemeier, David Friend, Ze Zhang, Diego Barba, Okyere Jeffrey Kwabena, Tyler Bohlke, Akil K. Sutton, Thomas Pham, Venkat Nammi, You Yang, Marquart Chad Andrew, Vikram Raj, Erik English, Dereje Yilma, James Crugnale
Publikováno v:
VLSI Circuits
This work presents an NRZ receiver (RX) implementation for microprocessor application in 7nm FinFET CMOS technology. It covers data rate from 25 to 50Gb/s and features on-chip AC coupling to support a wide input common-mode range. The RX includes two
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0e7b3acb75a042f60a39ae3387197c9
https://doi.org/10.1109/vlsicircuits18222.2020.9162821
https://doi.org/10.1109/vlsicircuits18222.2020.9162821
Autor:
Megan Nguyen, Brian Samuel Beaman, Dale Becker, Kevin M. McIlvain, Zhineng Fan, Junyan Tang, Biao Car, Abhijit Wander, Glen A. Wiedemeier, Hongqing Zhang, Sungjun Chun, Daniel M. Dreps, Brian J. Connolly, Zhaoqin Chen, Yifan Huang, Jose A. Hejase, Victor Mahran, Kyle Giesen, Baughen Devon
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
DDR5 Differential DIMM (DDIMM) is being defined in JEDEC and uses OMI as a host interface with the data transfer rate per data differential pair being specified at 25.6Gb/s minimum at present and at 51.2Gb/s maximum in the future. This is a significa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9e9136c15f300b3bc939a6c76c3ccc5b
https://doi.org/10.1109/ectc32862.2020.00158
https://doi.org/10.1109/ectc32862.2020.00158
Autor:
David Hogenmiller, Pierce Chuang, Saiful Islam, Ricardo Escobar, Daniel Lewis, Joshua Friedrich, Donald W. Plass, Rahul M. Rao, Pawel Owczarczyk, Paul H. Muench, Eric Fluhr, Michael A. Sperling, Juergen Pille, Vinod Ramadurai, Jose Angel Paredes, Michael Stephen Floyd, Christopher Gonzalez, Phillip J. Restle, Timothy Diemoz, Ryan Nett, Christos Vezyrtis, Ryan Kruse, Daniel M. Dreps
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:91-101
The POWER9TM family of chips is fabricated in 14-nm silicon-on-insulator finFET technology using 17 levels of copper interconnect. The 695-mm2 24-core microprocessor features a new core based on an execution slice microarchitecture. The chip contains
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b59f373baf8700ef174fb1e1577d6a63
https://doi.org/10.1109/jssc.2017.2748623
https://doi.org/10.1109/jssc.2017.2748623
Autor:
Yanyan Zhang, Pavel Roy Paladhi, Sungjun Chun, Lei Shan, Jose A. Hejase, Jean Audet, Mahesh Bohra, Wiren D. Becker, Daniel M. Dreps
Publikováno v:
2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
A novel edge card connector design approach with tunable signal integrity (SI) properties is proposed. The tunability is achieved through the presence or absence of a grounded conductive fixture in between the connector pin rows. The main purpose of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64736c919272eb2e598c24d0968f5c23
https://doi.org/10.1109/epeps47316.2019.193238
https://doi.org/10.1109/epeps47316.2019.193238
Autor:
Joshua C. Myers, Daniel M. Dreps, Prasanna Jayaraman, Wiren D. Becker, Junyan Tang, Pavel Roy Paladhi, Yanyan Zhang, Nam H. Pham, Sungjun Chun, Jose A. Hejase
Publikováno v:
2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
While equalization is usually a positively contributing factor towards opening eye diagrams further, sometimes over equalization can occur and degrade an eye opening as opposed to improve it. This paper explores the effectiveness of using post-cursor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e59a3349a92dbdbd36ef876f514eda04
https://doi.org/10.1109/epeps47316.2019.193221
https://doi.org/10.1109/epeps47316.2019.193221
Publikováno v:
2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
Effects of PCB wiring in tightly pitched module pin fields on high speed channel signal integrity are evaluated in this paper. Three different module orthogonal pin pitches are considered: 0.8mm, 1.06mm and 1.27mm. Each of the pin pitch scenarios is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce96992efe438aa5b216ec45d1cd1637
https://doi.org/10.1109/epeps47316.2019.193216
https://doi.org/10.1109/epeps47316.2019.193216