Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Daniel Claire Baker"'
Publikováno v:
Microelectronic Engineering. 35:517-522
One of the critical applications of DUV (248nm) lithography for 0.25 μm technology is the imaging of contact and via holes. The goal of this work was to demonstrate and verify manufacturing process capability for imaging 0.25 μm design rule (300 nm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a535df6599a1cf6a18214ee48668ecc
https://doi.org/10.1016/s0167-9317(96)00200-6
https://doi.org/10.1016/s0167-9317(96)00200-6
Autor:
Dipankar Pramanik, Daniel Claire Baker, Vivek Jain, Milind Weling, J. Eakin, William J. Boardman, Calvin T. Gabriel
Publikováno v:
Microelectronics Journal. 25:xviii-xxv
This paper describes a 0.6 micron triple level interconnect scheme for ASIC application. This interconnect scheme has been used with 0.6 micron twin well CMOS technology having polycide gates. Excellent planarization of BPSG films was achieved at a l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ace85a8a527b5dc5de7c8aebf7741b9
https://doi.org/10.1016/0026-2692(94)90174-0
https://doi.org/10.1016/0026-2692(94)90174-0
Publikováno v:
MRS Proceedings. 514
Advanced interconnect fabrication may require alternative TiITiN processes, such as an ionized metal plasma (IMP) sputtering technique to deposit Ti/TiN liner for sufficient step coverage in high aspect ratio contacts/vias. Since TiN is also widely u
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4eb15a82ef723a5421cd76382ef5bcef
https://doi.org/10.1557/proc-514-539
https://doi.org/10.1557/proc-514-539
Autor:
Kurt G. Ronse, Harry Botermans, Kouros Ghandehari, Peter De Bisschop, Luc Van den Hove, Maaike Op de Beeck, John A. Lilygren, Jo Finders, Daniel Claire Baker, Mireille Maenhoudt, Patrick Jaenen, Geert Vandenberghe
Publikováno v:
SPIE Proceedings.
In this paper, the results of an NA-sigma optimisation study are reported, carried out experimentally for an advanced ASML PAS5500/300 deep-UV stepper. The work has been primarily focused on a 0.25 and sub-0.25 mu m gate layer in a logic CMOS process
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::270f39e013a213d90086607d05f554bf
https://doi.org/10.1117/12.275973
https://doi.org/10.1117/12.275973
Publikováno v:
SPIE Proceedings.
Because of the tighter linewidth control requirements for 0.35 micrometer gate, adequate critical dimension control could not be achieved with a single layer photoresist. A top-side anti-reflective coating (TARC) was found to have limited line width
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aace6c9fc771bbe621a42e84a908c291
https://doi.org/10.1117/12.241869
https://doi.org/10.1117/12.241869
Publikováno v:
SPIE Proceedings.
Submicron photolithographic processes present significant manufacturing challenges due to the relatively small process windows often found with these technologies. Small upstream variations in the pre-expose portion of the photomodule or subtle radia
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::09815de64b30a0c216f4eb7840884b18
https://doi.org/10.1117/12.20074
https://doi.org/10.1117/12.20074