Zobrazeno 1 - 10
of 40
pro vyhledávání: '"Daniel Chaver"'
Publikováno v:
Journal of Computer Science and Technology, Vol 8, Iss 03, Pp 132-138 (2008)
One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex
Externí odkaz:
https://doaj.org/article/d61ecc29be0347399226fb2a4f204104
Autor:
Sarah L. Harris, Jose I. Gomez-Perez, Zubair L. Kakakhel, Olof Kindgren, Daniel Chaver, M. Hamza Liaqat, Luis Piñuel, Robert Owen
Publikováno v:
FPL
RISC-V FPGA, also written RVfpga, is a set of two freely available courses developed by the authors and Imagination Technologies that enable users to understand and use the RISC-V instruction set architecture (ISA), a commercial RISC-V core and syste
Autor:
Enrique Sedano, Yuri Panchul, Robert Owen, Sarah L. Harris, Daniel Chaver, Bruce Ableidinger, Zubair L. Kakakhel, David Harris
Publikováno v:
IET Circuits, Devices & Systems. 11:283-291
In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor
Publikováno v:
CIC Digital (CICBA)
Comisión de Investigaciones Científicas de la Provincia de Buenos Aires
instacron:CICBA
Comisión de Investigaciones Científicas de la Provincia de Buenos Aires
instacron:CICBA
Single-ISA asymmetric multicore processors (AMPs), which combine high-performance big cores with low-power small cores, were shown to deliver higher performance per watt than symmetric CMPs (Chip Multi-Processors). Previous work has highlighted that
Uso de la infraestructura docente MIPSfpga v2.0 en la asignatura Arquitectura de Sistemas Integrados
Autor:
Bruce Ableidinger, Daniel Chaver, Robert Owen, Yuri Panchul, David Harris, Zubair L. Kakakhel, Sarah L. Harris, Enrique Sedano
Publikováno v:
Enseñanza y Aprendizaje de Ingeniería de Computadores.
Este paper se basa en un artículo anterior titulado ”Practical experiences based on MIPSfpga”, publicado en el Workshop on Computer Architecture Education (celebrado en la conferencia ISCA-2017). Incluye algunas modificaciones: (1) Hemos ampliad
Autor:
Sarah L. Harris, Enrique Sedano, Bruce Ableidinger, Robert Owen, Zubair L. Kakakhel, David Harris, Yuri Panchul, Daniel Chaver
Publikováno v:
Proceedings of the 19th Workshop on Computer Architecture Education.
In this paper we describe how to use MIPSfpga, a soft-core MIPS processor, to teach undergraduate and masters-level computer architecture courses. The most recent release of MIPSfpga (version 2.0), consists of three packages: the MIPSfpga Getting Sta
Autor:
Javier Díaz, Manuel Prieto-Matias, Fernando Castro, Juan Carlos Saez, Pablo Ibáñez, Daniel Chaver, Roberto Rodríguez-Rodríguez, José M. Llabería, Luis Piñuel, Teresa Monreal, Víctor Viñals
Publikováno v:
Zaguán. Repositorio Digital de la Universidad de Zaragoza
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently postulated as the prime con
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1ccb03074f5d02c6d914ce6ffff9292a
http://zaguan.unizar.es/record/84317
http://zaguan.unizar.es/record/84317
Autor:
L. Piuel, Michael C. Huang, Fernando Castro, Francisco Tirado, R. Noor, Alok Garg, Daniel Chaver, Manuel Prieto
Publikováno v:
IEEE Transactions on Computers. 58:496-511
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-order execution. Traditional age-ordered associative load queues are comp
Publikováno v:
Journal of Systems Architecture. 55:79-89
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-order execution. Traditional age-ordered associative load and store queue
Publikováno v:
SAC
Single-ISA (instruction set architecture) asymmetric multicore processors (AMPs) were shown to deliver higher performance per watt and area than symmetric CMPs (Chip Multi-Processors) for applications with diverse architectural requirements. A large