Zobrazeno 1 - 10
of 119
pro vyhledávání: '"Dan Mocuta"'
Autor:
Yashwanth Balaji, Quentin Smets, Cesar Javier Lockhart De La Rosa, Anh Khoa Augustin Lu, Daniele Chiappe, Tarun Agarwal, Dennis H. C. Lin, Cedric Huyghebaert, Iuliana Radu, Dan Mocuta, Guido Groeseneken
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 6, Pp 1048-1055 (2018)
2-D transition metal dichalcogenides (TMDs) are promising materials for CMOS application due to their ultrathin channel with excellent electrostatic control. TMDs are especially well suited for tunneling field-effect transistors (TFETs) due to their
Externí odkaz:
https://doaj.org/article/b3e6abfea7bb4f1db4bad4d5dfcd0818
Autor:
Yida Li, Alireza Alian, Maheswari Sivan, Li Huang, Kah Wee Ang, Dennis Lin, Dan Mocuta, Nadine Collaert, Aaron V.-Y. Thean
Publikováno v:
APL Materials, Vol 7, Iss 3, Pp 031503-031503-8 (2019)
An ultra-thin (15 nm) InGaAs nanomembrane field-effect phototransistor is transferred entirely from a rigid InP substrate onto a flexible SU-8 on a polydimethylsiloxane substrate. The transferred InGaAs device exhibits wide-band spectral response tun
Externí odkaz:
https://doaj.org/article/f77f7facc024464f890d9e1b54183d83
Publikováno v:
AIP Advances, Vol 8, Iss 5, Pp 055920-055920-6 (2018)
Spin Torque Majority Gate (STMG) is a logic concept that inherits the non-volatility and the compact size of MRAM devices. In the original STMG design, the operating range was restricted to very small size and anisotropy, due to the exchange-driven c
Externí odkaz:
https://doaj.org/article/6c8fa8896e7848d6a00431c74b5e5aea
Autor:
Mauricio Manfrini, Adrien Vaysset, Danny Wan, Eline Raymenants, Johan Swerts, Siddharth Rao, Odysseas Zografos, Laurent Souriau, Khashayar Babaei Gavan, Nouredine Rassoul, Dunja Radisic, Miroslav Cupak, Morin Dehan, Safak Sayan, Dmitri E. Nikonov, Sasikanth Manipatruni, Ian A. Young, Dan Mocuta, Iuliana P. Radu
Publikováno v:
AIP Advances, Vol 8, Iss 5, Pp 055921-055921-6 (2018)
With the rapid progress of spintronic devices, spin-logic concepts hold promises of energy-delay conscious computation for efficient logic gate operations. We report on the electrical characterization of domain walls in interconnected magnetic tunnel
Externí odkaz:
https://doaj.org/article/3f5c305de3ab449fb4b079fd3d74e315
Autor:
Guillaume Boccardi, Hiroaki Arimura, Roger Loo, Samuel Suhard, Daire J. Cott, Thierry Conard, Naoto Horiguchi, L.-A. Ragnarsson, V. De Heyn, Jerome Mitard, Dan Mocuta, Liesbeth Witters, H. Dekkers, D. H. van Dorp, Nadine Collaert, Kurt Wostyn
Publikováno v:
IEEE Transactions on Electron Devices. 66:5387-5392
This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high- ${k}$ last process. SiO2 dummy gate oxide (D
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1dd5f23cc243b67badeb99d80e2e88e1
https://doi.org/10.1109/ted.2019.2950332
https://doi.org/10.1109/ted.2019.2950332
Autor:
Yves Mols, Clement Merckling, A. Vais, Dan Mocuta, Siva Ramesh, Hao Yu, Nadine Collaert, Kristin De Meyer, Marc Schaekers, Naoto Horiguchi, Tsvetan Ivanov, Lin-Lin Wang, Jian Zhang, Yu-Long Jiang
Publikováno v:
IEEE Electron Device Letters. 40:1800-1803
We compare the contact characteristics for Mo, Pd, and Ti on n-InGaAs layer with a range of active donor concentration from $1.6 \times 10^{18}$ cm−3 to $4.8 \times 10^{19}$ cm−3. The Fermi level pinning of 0.18 eV lower than the bottom of n-InGa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d63880b9dac2b584aa0e1ef62530474b
https://doi.org/10.1109/led.2019.2944245
https://doi.org/10.1109/led.2019.2944245
Autor:
Kristin De Meyer, Hao Yu, Nadine Collaert, Jean-Luc Everaert, Marc Schaekers, Naoto Horiguchi, Lin-Lin Wang, Dan Mocuta, Yu-Long Jiang
Publikováno v:
IEEE Electron Device Letters. 40:1712-1715
Presence of a native oxide interlayer degrades seriously the contact resistivity ( $\rho _{{\text {c}}}$ ) of co-deposited TiSi (CD-TiSi) on Si:P. The oxide cannot be scavenged by the CD-TSi due to its low solid solubility of O. We tackle the problem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::557556af834a734eeee8b4188061c860
https://doi.org/10.1109/led.2019.2940819
https://doi.org/10.1109/led.2019.2940819
Autor:
Rogier Baert, Philippe Roussel, Kristof Croes, Antonino Contino, Zsolt Tokei, Dan Mocuta, Ivan Ciofi, Christopher J. Wilson, Anshul Gupta
Publikováno v:
IEEE Transactions on Electron Devices. 66:2339-2345
We address RC scaling trends and predict the performance benefits of advanced metallization options with respect to conventional Cu/low- ${k}$ interconnects. The range of interconnect dimensions we cover spans from the 22 nm to the 3 nm logic technol
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::45a2aa18c1b1559c2b769c705d689770
https://doi.org/10.1109/ted.2019.2902031
https://doi.org/10.1109/ted.2019.2902031
Autor:
Stefan Kubicek, Naushad Variam, Pierre Eyben, Y. Kikuchi, Dan Mocuta, Naoto Horiguchi, A. Waite, T. Hopf, Jose Ignacio del Agua Borniquel, Geert Mannaert, Jean-Luc Everaert
Publikováno v:
Solid-State Electronics. 152:58-64
In this paper, high temperature Phosphorus ion implantation is applied to p-type Si (1 0 0) substrates and n-type bulk Si fin field-effect-transistors. Phosphorus profiles and sheet resistance on p-type Si (1 0 0) substrates are analyzed. High temper
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3f1356145d1795e6d0c7befed84957ca
https://doi.org/10.1016/j.sse.2018.11.003
https://doi.org/10.1016/j.sse.2018.11.003
Autor:
Amey Mahadev Walke, Anne Vandooren, F. M. Bufler, Nancy Heylen, J. Franco, Bich-Yen Nguyen, Gweltaz Gaudin, Lieve Teugels, Veeresh Deshpande, Boon Teik Chan, Dan Mocuta, Walter Schwarzenbach, T. Zheng, W. Li, Z. Wu, Erik Rosseel, Niamh Waldron, Nadine Collaert, E. Vecchio, Nouredine Rassoul, Romain Ritzenthaler, V. De Heyn, Bertrand Parvais, W. Vanherle, Liesbeth Witters, Iuliana Radu, G. Verbinnen, Lan Peng, Fumihiro Inoue, Andriy Hikavyy, Geert Hellings, Katia Devriendt, G. Jamieson, G. Besnard
Publikováno v:
IEEE Transactions on Electron Devices. 65:5165-5171
3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92b4a10dc727e8fb50bf8a9778c9db9e
https://doi.org/10.1109/ted.2018.2871265
https://doi.org/10.1109/ted.2018.2871265