High-yield design of high-density SRAM for low-voltage and low-leakage operations

Autor: Hitesh Chawla, Prashant Pandey, Damien Croain, Lorenzo Ciampolini, Ashish Kumar, Promod Kumar, Florian Cacho, Kedar Janardan Dhori

Publikováno v: DFT

The minimum functional voltage of System-On-Chip manufactured in recent technology nodes is often that of its Static Random-Access Memories (SRAM). Operating SRAM at subnominal voltage requires the use of additional circuits named assist circuits. Th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a59bbdade3c655dd4ceb8092cc86a294
https://doi.org/10.1109/dft.2017.8244429

A 28nm FD-SOI Standard Cell 0.6-1.2V Open-Loop Frequency Multiplier for Low Power SoC Clocking

Autor: Martin Cochet, Jean-Luc Autran, Pierre Schamberger, Damien Croain, Philipe Roche, Mehdi Naceur, Sylvain Clerc

Publikováno v: 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, Unknown, Unknown Region. pp.1206-1209
ISCAS

IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016; International audience; This paper presents a new design for SoC clocking based on open-loop frequency multiplication. The architecture, fully implemente

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b7ebb358cf4bf76ad3de4d2c27366343
https://hal.archives-ouvertes.fr/hal-01434957

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing

Autor: Pierre Schamberger, Fady Abouzeid, Martin Cochet, Mehdi Saligane, Dennis Sylvester, Dominique Zamora, Benjamin Coeffic, Cyril Bottoni, Julien De-Vos, Philippe Roche, Jean-Marc Daveau, Mehdi Naceur, Damien Croain, David Bol, Sylvain Clerc, Dimitri Soussan

Publikováno v: ISSCC

A 32b SoC is designed in 28nm FDSOI to operate in either an energy-efficiency (EE) mode, at 0.45V, or low-leakage (LL) mode, at 0.33V, with process-temperature compensation. At near threshold, it overcomes low transistor current at negative temperatu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::126894589e4ab4f952aef26653ef1d36
https://doi.org/10.1109/isscc.2015.7062970

A predictive bottom-up hierarchical approach to digital system reliability

Autor: V. Robert, Sylvain Engels, Philippe Flatresse, Florian Cacho, P. Mergault, Lorena Anghel, R. Delater, Vincent Huard, Damien Croain, E. Pion, N. Ruiz Amador

Publikováno v: Proc. of IEEE International Reliability Physics Symposium (IRPS'12)
IEEE International Reliability Physics Symposium (IRPS'12)
IEEE International Reliability Physics Symposium (IRPS'12), Apr 2012, Anaheim, CA, United States. pp.4B.1.1-4B.1.10, ⟨10.1109/IRPS.2012.6241830⟩

ISBN 978-1-4577-1678-2; This paper has been granted the OUTSTANDING PAPER AWARD; International audience; This work has introduced a new electrical aging assessment framework for digital systems, based upon strong physics-based foundations and an adeq

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f1cb61defe9a1b568b1e53fe62c3a46f
https://hal.archives-ouvertes.fr/hal-00747363

Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec

Autor: Pascal Urard, Philippe Flatresse, Alexandre Valentian, Julien Le Coz, Damien Croain, Christine Raynaud, Marc Belleville, Sylvain Engels

Publikováno v: ISSCC

A Low-Density Parity-Check (LDPC) codec circuit is implemented in a 65nm Low-Power Partially-Depleted SOI (LP PD-SOI) technology, as well as in a “conventional” Low-Power Bulk technology for a fair comparison. PD-SOI allows to increase maximum fr

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::11200d25da7da77ff09f8f50d4e312a2
https://doi.org/10.1109/isscc.2011.5746343