Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Dale E. Pontius"'
Autor:
Darren L. Anand, S. Sliva, Jeffrey H. Dreibelbis, Dale E. Pontius, Michael R. Nelms, Erik A. Nelson, S. Burns, Kevin W. Gorman, Adrian J. Paparelli, John E. Barth, G. Pomichter, John A. Fifield
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:213-222
This work describes a 500-MHz compiled eDRAM macro offered in a 90-nm logic-based process. The macro architecture is optimized for high bandwidth while enabling compilation in bank and data-word dimensions. A direct write scheme simultaneously improv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01a70e212ab54fca80057305bcaab0c8
https://doi.org/10.1109/jssc.2004.838001
https://doi.org/10.1109/jssc.2004.838001
Autor:
Mark D. Jacunski, P. K. Lane, Michael A. Roberge, Dale E. Pontius, S. Sliva, John A. Fifield, Robert E. Busch, Adrian J. Paparelli, Darren L. Anand, Gary Pomichter, Matthew C. Lanahan
Publikováno v:
CICC
A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for V DD = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank mo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14d31cabf0d4ccfd61c6807436dc9d6c
https://doi.org/10.1109/cicc.2010.5617634
https://doi.org/10.1109/cicc.2010.5617634
Autor:
J. Paparelli, John A. Fifield, Dale E. Pontius, Michael A. Roberge, S. Sliva, Kevin W. Gorman, Jeffrey H. Dreibelbis, Darren L. Anand, J. Covino, G. Pomichter, Mark D. Jacunski
Publikováno v:
CICC
An embedded DRAM macro fabricated in 65 nm CMOS achieves 1.0 GHz multi-banked operation at 1.0 V yielding 584 Gbits/sec. The array utilizes a 0.1 1 mum2 cell with 20 fF deep trench capacitor and 2.2 nm gate oxide transfer gate. Concurrent refresh all
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14541abf360e7654127a45f03b2a7e54
https://doi.org/10.1109/cicc.2007.4405849
https://doi.org/10.1109/cicc.2007.4405849
Autor:
G. Fredernan, Dale E. Pontius, Chomg-Lii Hwang, S. W. Tomashot, Toshiaki Kirihata, M. Wordernan, D. Storaska, Sang Hoo Dhong, Brian L. Ji, John A. Fifield
Publikováno v:
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
High performance devices available in a logic-based embedded DRAM process can be used to significantly improve eDRAM performance. However, random access cycle time of conventional eDRAMs remains around 6 ns. In this work, a novel destructive-read arc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::47cd0320334aacb85fa7087492876352
https://doi.org/10.1109/vlsic.2002.1015077
https://doi.org/10.1109/vlsic.2002.1015077