Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Dai Hoon Lee"'
Autor:
Dai-Hoon Lee
Publikováno v:
Integrated Ferroelectrics. 17:113-126
For more than decade, DRAM has been serving as the technology driver of semiconductor industry and, for the time being, it seems to play the similar role past the year 2000. This can be typically exemplified by lithography evolution which has evolved
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ccb0bd7d12e4544d66336e3ae1bc64fa
https://doi.org/10.1080/10584589708012987
https://doi.org/10.1080/10584589708012987
Autor:
Yu Liu, Wen Cheng Xiong, Dai Hoon Lee, Jiau Xiu Xie, Cai Xia Xi, Li Juau Zhou, Zheng Zhou, Lin Mei, Ji-Ung Jung
Neogenin, a deleted in colorectal cancer (DCC) family member, has been identified as a receptor for the neuronal axon guidance cues netrins and repulsive guidance molecules repulsive guidance molecules (RGM). RGMc, also called hemojuvelin (HJV), is e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::376cb12fa800c738647df8403ee1ce11
https://europepmc.org/articles/PMC2858467/
https://europepmc.org/articles/PMC2858467/
Publikováno v:
SPIE Proceedings.
In this paper, we demonstrated the impact of illumination condition on MEEF and investigated the correlation between CD linearity and MEEF according to the illumination conditions and imaging pitches. For all of the illumination conditions, the MEEF
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::36e8237d19d2c10ffba948cd1dc5537a
https://doi.org/10.1117/12.485514
https://doi.org/10.1117/12.485514
Publikováno v:
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).
Model based full chip Optical Proximity Correction (OPC) was applied to logic devices with a minimum gate length of 0.24 /spl mu/m. Two empirical models were used in order to correct for both the 1D optical proximity effect and the 2D optical proximi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a554c3c77e73bac499d9bb4599686683
https://doi.org/10.1109/icvc.1999.820864
https://doi.org/10.1109/icvc.1999.820864
Autor:
Jeong-Kug Lee, Hyung-Suk Kim, Jongwook Lee, Ji-Woon Yang, Myung-Jun Chung, Won-Chul Lee, Min-Rok Oh, Jeong-Yun Yang, Kyoung-Wook Park, Won-Chang Lee, Kwang-Ho Ahn, Jae-Beom Park, Hyung-Ki Kim, Dai-Hoon Lee, Kyung-Suk Choi, Yo-Hwan Koh, Kwang-Myung Rho, In-Seok Hwang, Yeon-Cheol Heo, Chan-Kwang Park, Min Huh, Byung-Cheol Lee
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
1 Gbit SOI DRAM with a body-contacted (BC) SOI MOSFET structure is successfully realized for the first time. The fabricated 1G SOI DRAM has fully compatible process with 0.17 /spl mu/m bulk CMOS technology except for the isolation process. The key ad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e7af2b3e46473d4a8e6f56bdb6e3bba
https://doi.org/10.1109/iedm.1997.650451
https://doi.org/10.1109/iedm.1997.650451
Autor:
Myoung Jun Chung, Yo Hwan Koh, Kwang Myoung Rho, Chan Kwang Park, Ha Poong Chung, Dai Hoon Lee, Seong Min Hwang
Publikováno v:
1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings.
With the MOSES (Mask Oxide Sidewall Etch Scheme) process which uses a conventional i-line stepper and isotropic wet etching, CMOSFETs with fine gate patterns of 0.1 /spl mu/m or less are fabricated and characterized successfully. To improve the short
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3630e9adc127e188d06a144c523ecd2e
https://doi.org/10.1109/tencon.1995.496397
https://doi.org/10.1109/tencon.1995.496397
Autor:
Kwang Myoung Rho, Yo Hwan Koh, Seong Min Hwang, Dai-Hoon Lee, Chan Kwang Park, Myoung Jun Chung
Publikováno v:
1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers.
A novel structure for high performance deep submicron MOSFETs, which is called the SAW (Self-Aligned selectively grown W-gate) MOSFET, is proposed. The SAW MOSFET structure has extremely low gate resistance due to the use of tungsten as gate electrod
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fbe645ebb20254f71a6bcafe54bd57b
https://doi.org/10.1109/vtsa.1995.524701
https://doi.org/10.1109/vtsa.1995.524701
Publikováno v:
Proceedings International Conference on Microelectronic Test Structures.
A new CV method is proposed to determine the metallurgical gate-to-source/drain overlap length of LDD MOSFETs. In addition, the flatband voltage is extracted roughly by using the same method. The gate-to-substrate capacitances of a plate gate capacit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de7c6617221ac7b25c3047f68e9fe7ad
https://doi.org/10.1109/icmts.1995.513963
https://doi.org/10.1109/icmts.1995.513963
Publikováno v:
SPIE Proceedings.
In this paper, we will describe why the calibration process between CD-SEM and transmission electron microscopy (TEM) was performed. TEM is considered to be a unique solution such that we could obtain CD and sidewall angle accurately. TEM has the mer
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72c749a32966d8b222e78310696a7ab7
https://doi.org/10.1117/12.473519
https://doi.org/10.1117/12.473519
Publikováno v:
Advances in Resist Technology and Processing XVII.
The bi-layer resist (BLR) process, which first accomplish imaging on a thin top layer and transfer it down to a thick organic layer, is one of newly emerging patterning techniques in silicon processing. In this work, we studied the lithographic perfo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::263c61380483d8ad826c5a7fcbac547f
https://doi.org/10.1117/12.388368
https://doi.org/10.1117/12.388368