Zobrazeno 1 - 10
of 742
pro vyhledávání: '"DPLL algorithm"'
Autor:
Jose J. Paulet, Luis F. LLana, Hernán Indíbil Calvo, Mauro Mezzini, Fernando Cuartero, Fernando L. Pelayo
Publikováno v:
Mathematics, Vol 11, Iss 8, p 1888 (2023)
The SAT problem is maybe one of the most famous NP-complete problems. This paper deals with the 3-SAT problem. We follow a sort of incremental strategy to save computational costs with respect to the classical quantum computing approach. We present a
Externí odkaz:
https://doaj.org/article/9d4ea93bb2ed459fb489125de18a5c97
Publikováno v:
IEEE Transactions on Transportation Electrification. 8:1267-1277
In order to get rid of the chattering problem of sliding mode observer, this article presents an adaptive sliding mode observer (ASMO)-based sensorless control for surface-mounted permanent-magnet synchronous machines (SPMSM). In the conventional sli
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:264-268
This brief analyzes a linear characteristic of the highresolution counter-based frequency detector (CBFD) using sinusoidal jitter. The theoretical gain of the Vernier-type CBFD can be derived by observing the output responses for the tone input in th
Autor:
Ooh Ufuoma
The goal of this work is to modify the famous DPLL algorithm to solve all SATs in polynomial time.
This work discusses a polynomial time algorithm for solving ALL SATs.
{"references":["Aaronson S. and Wigderson A., Algebrization: a new barr
This work discusses a polynomial time algorithm for solving ALL SATs.
{"references":["Aaronson S. and Wigderson A., Algebrization: a new barr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::11958fb63f19a446abc418dbd1d80710
Akademický článek
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Publikováno v:
IEEE Journal of Solid-State Circuits. 56:1254-1264
This article presents a power-efficient low-jitter fractional-N digital phase-locked loop (DPLL) that resolves phase error (PE) in the fully differential voltage (FDV) domain. Compared with adopting a traditional time-to-digital converter (TDC), whic
Publikováno v:
International Journal of Naval Architecture and Ocean Engineering, Vol 13, Iss, Pp 617-627 (2021)
Underwater Acoustic Channels (UAC) have inherent sparse characteristics. The traditional adaptive equalization techniques do not utilize this feature to improve the performance. In this paper we consider the Variable Adaptive Subgradient Projection (
Publikováno v:
IEEE Journal of Solid State Circuits, 57(6)
In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply
Autor:
Fenzel, Petra
Obwohl nicht gleich offensichtlich hat eine Ponyfarm ein ähnliches Terminplanungsproblem wie zum Beispiel eine Schule, die ihre Ressourcen entsprechend zuordnen muss. Digitale Lösungen berücksichtigen derzeit bei der Zuweisung immer nur Teile der
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_____10650::6db7fbf536e6f6223cd9b5dafdb09919
Autor:
Fenzel, Petra
SAT Solver sind in aller Munde, wenn es um Methoden geht, um Boolesche Erfüllbarkeitsprobleme zu lösen. Es gibt sogar eine SAT Association, die jährliche, internationale Konferenzen abhält, um die Forschung auf diesem Gebiet voranzutreiben. Diese
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_____10650::6d950dc90626fe5b8f8edaf5848d1d85