Zobrazeno 1 - 10
of 228
pro vyhledávání: '"D.W. Clark"'
Autor:
Daniel A. Connors, Qiang Wu, Vijay Janapa Reddi, Jaekyu Lee, David Brooks, Youfeng Wu, D.W. Clark, Margaret Martonosi
Publikováno v:
IEEE Micro. 26:119-129
A general dynamic-compilation environment offers power and performance control opportunities for microprocessors. The authors propose a dynamic-compiler-driven runtime voltage and frequency optimizer. A prototype of their design, implemented and depl
Publikováno v:
IEEE Micro. 25:52-62
These techniques determine when to speed up a processor to reach performance targets and when to slow it down to save energy. They use dynamic voltage and frequency scaling to balance speed and avoid worst case frequency limitations for both multiple
Autor:
Rudrajit Samanta, Han Chen, Matthew A. Hibbs, Grant Wallace, Anoop Gupta, Kai Li, P. Bi, Thomas Funkhouser, Zicheng Liu, Yuqun Chen, Otto J. Anshus, Adam Finkelstein, Perry R. Cook, D.W. Clark, Olga G. Troyanskaya, Rahul Sukthankar
Publikováno v:
IEEE Computer Graphics and Applications. 25:24-33
Increased processor and storage capacities have supported the computational sciences, but have simultaneously unleashed a data avalanche on the scientific community. As a result, scientific research is limited by data analysis and visualization capab
Akademický článek
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Publikováno v:
Injury. 22:89-92
The introduction of the reconstruction nail has broadened the indications for the intramedullary fixation of difficult femoral fractures. The operative technique is, however, complicated. Some technical difficulties encountered during its use are pre
Autor:
Vijay Janapa Reddi, D.W. Clark, Youfeng Wu, Jin Lee, Margaret Martonosi, David Brooks, Qiang Wu, Daniel A. Connors
Publikováno v:
MICRO
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS time-interrupts, or static-compiler techniques. However, substa
Akademický článek
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Publikováno v:
ISLPED
Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. However, to date, no power management techniques have been proposed for coordinated powe
Publikováno v:
International Symposium on Code Generation and Optimization, 2004. CGO 2004..
Autor:
M.A. Blumrich, R.D. Alpert, null Yuqun Chen, D.W. Clark, S.M. Damianakis, C. Dubnicki, E.W. Felten, L. Iftode, K. Li, M. Martonosi, R.A. Shillner
Publikováno v:
Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235).