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pro vyhledávání: '"D.M.H. Walker"'
Akademický článek
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Publikováno v:
IEEE Transactions on Computers. 47:1136-1152
This paper presents an I/sub DDQ/-based test strategy for detecting bridging faults in the logic resources of reprogrammable field programmable gate arrays (FPGAs). The proposed approach utilizes the programmability of the configurable logic blocks (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::985775cf7cf74e41cf12871969eef1e2
https://doi.org/10.1109/12.729796
https://doi.org/10.1109/12.729796
Autor:
W.C. Dietrich, V.T. Rajan, M.E. Law, R.H. Wang, G.R. Chin, P.K. Mozumder, M.D. Giles, M.S. Karasick, L.R. Nackman, D.M.H. Walker, A.S. Wong, Duane S. Boning
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 13:82-95
This work describes the Semiconductor Wafer Representation (SWR) for representing and manipulating wafer state during process and device simulation. The goal of the SWR is to provide an object-oriented interface to a collection of functions designed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b6955a4da38b1996b68abd62a6e220bd
https://doi.org/10.1109/43.273747
https://doi.org/10.1109/43.273747
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 12:283-295
The chip database (CDB) and the hierarchical chip database (HCDB) and their uses in a wafer representation server are described. The server provides data types and methods for hierarchically representing the three-dimensional geometry and fields of a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dd5c81f57831a269c422864a4d3c0c07
https://doi.org/10.1109/43.205008
https://doi.org/10.1109/43.205008
Akademický článek
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Autor:
Daniel S. Nydick, D.M.H. Walker
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 9:655-664
Simulation of local process disturbances is a computationally intensive task. The VLASIC (VLSI LAyout Simulation for Integrated Circuits) catastrophic-fault yield simulator uses a Monte Carlo method that often requires tens of CPU hours to perform a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a21a8c7e1ad72fccda2704a871b2808e
https://doi.org/10.1109/43.55195
https://doi.org/10.1109/43.55195
Autor:
Eunjae Jung, D.M.H. Walker
Publikováno v:
MASS
This paper describes algorithms for creation and maintenance of a spanning tree connecting nodes to the central observer (root) in wireless sensor networks. The tree is dynamically reconfigured to route around failed nodes, while minimizing energy co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2483b4fea4da2803d7846f99a9261f7f
https://doi.org/10.1109/mahss.2005.1542808
https://doi.org/10.1109/mahss.2005.1542808
Autor:
P.K. Mozumder, D. Bonning, N. Khalil, W.C. Dietrich, R. Cottle, R. Tremain, A.S. Wong, M.D. Giles, D.M.H. Walker, R. Harris, Sani R. Nassif, D. Schroeder, V.T. Rajan, M.E. Law, M.S. Karasick, L.R. Nackman, S. Duvall, G.R. Chin, R.H. Wang, M.J. McLennan
Publikováno v:
NUPAD IV. Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34f3ce0c10c4c90c55abbcdda25e9309
https://doi.org/10.1109/nupad.1992.674104
https://doi.org/10.1109/nupad.1992.674104
Autor:
D.M.H. Walker, S.S. Sabade
Publikováno v:
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004).
Extending the useful life of I/sub DDQ/ test to deep submicron technologies has been a topic of interest in recent years. I/sub DDQ/ test loses its effectiveness as the signal to noise ratio degrades due to rising background current and fault-free I/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::371bd44f3b35206e95bdd3ec1bb804be
https://doi.org/10.1109/dbt.2004.1408947
https://doi.org/10.1109/dbt.2004.1408947
Publikováno v:
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bdcf928c32dcb4911cdfc5d837b88b76
https://doi.org/10.1109/aspdac.2004.1337547
https://doi.org/10.1109/aspdac.2004.1337547