Zobrazeno 1 - 10
of 69
pro vyhledávání: '"D.K. Banerji"'
Publikováno v:
Computer Communications. 34:548-555
Wireless mesh networks (WMNs) consist of dedicated nodes called mesh routers which relay the traffic generated by mesh clients over multi-hop paths. In a community WMN, all mesh routers may not be managed by an Internet Service Provider (ISP). Limite
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fef6edd4db09dc870b1ceb8dea252610
https://doi.org/10.1016/j.comcom.2010.04.040
https://doi.org/10.1016/j.comcom.2010.04.040
Publikováno v:
Canadian Journal of Electrical and Computer Engineering. 32:53-64
Field-programmable gate arrays (FPGAs) are semiconductor chips that can realize most digital circuits on site by specifying programmable logic and their interconnections. The use of FPGAs has grown almost exponentially because they dramatically reduc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::496664cd8693075ebb3e768489955657
https://doi.org/10.1109/cjece.2007.364333
https://doi.org/10.1109/cjece.2007.364333
Publikováno v:
Microelectronics Journal. 24:513-532
In this paper, we consider the problem of optimizing interconnection complexity in behavioral level synthesis of digital systems. We assume that, as a result of other steps in synthesis, logical connection requirements have already been determined, w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ee71578ec59d4931fdd4973f9b8a4c86
https://doi.org/10.1016/0026-2692(93)90120-4
https://doi.org/10.1016/0026-2692(93)90120-4
Publikováno v:
International Journal of Electronics. 73:417-431
Exploiting operator commutativity is used in high-level synthesis for reducing interconnections. The standard heuristic is to apply a succession of pairwise operand interchanges. We present a new and general characterization of the problem in terms o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7acd6e932aec1ac1a21fd7162258b818
https://doi.org/10.1080/00207219208925678
https://doi.org/10.1080/00207219208925678
Publikováno v:
CCECE
With rapid advances in integrated circuit technology, wirelength has become one of the most critical and important metrics in all phases of VLSI physical design automation, especially circuit placement. As the precise wirelength for a given placement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3404c9248483f7ddfbe05110bde422bb
https://doi.org/10.1109/ccece.2009.5090315
https://doi.org/10.1109/ccece.2009.5090315
Publikováno v:
CCECE
The Rectilinear Steiner Tree Problem (RSTP) is a classical problem having numerous real-world applications, including VLSI routing. Since the RSTP is NP-hard, developing polynomial heuristics which can produce near optimal solutions has been the prim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ef0e781557823c1511f55b547054167
https://doi.org/10.1109/ccece.2006.277830
https://doi.org/10.1109/ccece.2006.277830
Publikováno v:
VLSI Design
We present an optimum and integrated solution to the problems of scheduling, allocation, and binding using an integer linear program (UP) that minimizes a weighted sum of module area and total ezecution time under very general assumptions of module c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3f389b14610862ba6d312a97948a3c6
https://doi.org/10.1109/icvd.1993.669676
https://doi.org/10.1109/icvd.1993.669676
Publikováno v:
The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004..
The time to compile current field programmable gate arrays (FPGAs) can easily take hours or even days to complete for large (8-million gate) chips, which may nullify the time-to-market advantage of FPGAs. This paper presents a novel adaptive placemen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c16965ed03dd88483046307a7fded37e
https://doi.org/10.1109/newcas.2004.1359111
https://doi.org/10.1109/newcas.2004.1359111
Autor:
Zhibin Dai, D.K. Banerji
Publikováno v:
VLSI Design
Field Programmable Gate Arrays (FPGAs) have emerged as the key technology for rapidly implementing digital circuits in VLSI. Much research has been done on their architecture and applications. One particularly important area of study is their routing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f285498885a539aa4f9e38bd77aaf609
https://doi.org/10.1109/icvd.2003.1183119
https://doi.org/10.1109/icvd.2003.1183119
Publikováno v:
Proceedings of the 32nd Midwest Symposium on Circuits and Systems.
In order to optimally allocate multiport memories in datapath synthesis, registers are simultaneously assigned to a configuration of several memories; this gives a more uniform distribution of register activity across the memories and usually provide
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e65b995450c3f99427d1e0da9b135e48
https://doi.org/10.1109/mwscas.1989.102039
https://doi.org/10.1109/mwscas.1989.102039