Zobrazeno 1 - 10
of 115
pro vyhledávání: '"D.J. Kinniment"'
Publikováno v:
BASE-Bielefeld Academic Search Engine
Microelectronics Journal, 6, 42, 840-850
Microelectronics Journal, 6, 42, 840-850
Sub-threshold operation has been proven to be very effective to reduce the power consumption of circuits when high performance is not required. Future low power systems on chip are likely to consist of many sub-systems operating at different frequenc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7068117a01bda6235c4793f0b2320dbd
https://doi.org/10.1016/j.mejo.2011.04.008
https://doi.org/10.1016/j.mejo.2011.04.008
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:550-557
A deep metastability measurement scheme has been implemented on chip using digital circuits with 0.18 mum technology. Compared with previous off-chip implementations using analog circuits, the on-chip implementation allows integration of both the syn
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::840c1bccebe37e1723c78ebdc1114513
https://doi.org/10.1109/jssc.2007.913160
https://doi.org/10.1109/jssc.2007.913160
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15:1028-1039
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6809a08b5c02cd5597d26d8d1a137d56
https://doi.org/10.1109/tvlsi.2007.902207
https://doi.org/10.1109/tvlsi.2007.902207
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:202-209
Synchronizer circuits are usually characterized by their rate of failure in transmitting data between two independently timed regions. The mean time between failures (MTBF) is given. These effects can be explained by extending the existing theory to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bc8324d35da5d81b5b8b86b8c4596cee
https://doi.org/10.1109/4.982426
https://doi.org/10.1109/4.982426
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8:217-220
Analog-digital (A-D) converters with a fixed conversion time are subject to errors due to metastability. It is shown that an asynchronous converter in which the conversion time is not bounded is faster, on average, than the synchronous design. Real-t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5cded684e653b64386873de114344ac
https://doi.org/10.1109/92.831441
https://doi.org/10.1109/92.831441
Publikováno v:
Integration. 21:143-170
In this tutorial paper we survey some of the existing techniques for modelling, analysis and synthesis of asynchronous control circuits. All these methods are based on the use of Petri nets as a tool for describing the behaviour of such circuits. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00b95a58187ca67586522b6116256522
https://doi.org/10.1016/s0167-9260(96)00010-7
https://doi.org/10.1016/s0167-9260(96)00010-7
Autor:
D.J. Kinniment, E. Kappos
Publikováno v:
Microprocessors and Microsystems. 20:225-232
This paper illustrates certain design techniques and tradeoffs for application-specific processors by considering the design of fully integrated speed and torque controllers for electric motors. We begin with the algorithmic requirements of two contr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e995dc32945a54b5bf2bf5ed5a4daf26
https://doi.org/10.1016/0141-9331(96)01084-8
https://doi.org/10.1016/0141-9331(96)01084-8
Autor:
D.J. Kinniment
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 4:137-140
There is considerable interest at present in the design of asynchronous systems based on the use of self-timing components for arithmetic and other operations. Amongst the advantages claimed for asynchronous design are ease of design, high speed, low
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72cf5e9c76f36f1d31f489292a9f383d
https://doi.org/10.1109/92.486088
https://doi.org/10.1109/92.486088
Autor:
D.J. Kinniment, Manoel Eusebio de Lima
Publikováno v:
Microelectronics Journal. 26:431-440
This paper deals with the development of sea-of-gates technology for the design of VLSI circuits. Sea-of-gates technology, also considered a second generation gate-array system, is discussed in detail. Its internal structure and the main physical asp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1297f60aee2fabeb644725b5e2a836c0
https://doi.org/10.1016/0026-2692(95)98945-n
https://doi.org/10.1016/0026-2692(95)98945-n
Publikováno v:
2010 International Conference on Microelectronics.
The reliability of a synchronizer depends on its recovery time from metastability, a time which is reduced if the delay through the synchronizer flip flops is large. The D to Q delay in a dual edge triggered D flip flop based on wagging is lower than
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6575369048577234c2278cb3b3a5005
https://doi.org/10.1109/icm.2010.5696176
https://doi.org/10.1109/icm.2010.5696176