Zobrazeno 1 - 10
of 29
pro vyhledávání: '"D.C. Sekar"'
Publikováno v:
IEEE Transactions on Advanced Packaging. 33:79-87
Power dissipation in microprocessors is projected to reach a level that may necessitate chip-level liquid cooling in the near future. An on-chip microchannel heat sink can reduce the total thermal interfaces between an integrated circuit chip and the
Publikováno v:
IEEE Electron Device Letters. 28:767-769
It is well known that electromigration (EM) time-to-failure for ac is several orders of magnitude larger than for dc. We propose a novel technique that reverses current direction in the power delivery system of a microprocessor every time it is reboo
Publikováno v:
2008 IEEE Avionics, Fiber-Optics and Photonics Technology Conference.
Three-dimensional (3D) system integration is widely accepted as a key enabler for future systems. Although there are a number of approaches to 3D integration, none have addressed the need for cooling in a 3D stack of high-performance chips (microproc
Autor:
Calvin King, Gang Huang, Muhannad S. Bakir, B. Dang, Hiren D. Thacker, James D. Meindl, Azad Naeemi, D.C. Sekar
Publikováno v:
CICC
This paper describes a novel 3D integration technology that enables the integration of electrical, optical, and microfluidic interconnects in a 3D die stack. The electrical interconnects are used to provide power delivery and signaling, the optical i
Autor:
Paul F. Joseph, James D. Meindl, Todd J. Spencer, Hiren D. Thacker, B. Dang, D.C. Sekar, Muhannad S. Bakir, Calvin King
Publikováno v:
2008 International Interconnect Technology Conference.
A 3D-IC technology with integrated microchannel cooling is demonstrated in this paper. Fluidic interconnect network fabrication proceeds at the wafer-level, is compatible with CMOS processing and flip-chip assembly and requires four lithography steps
Publikováno v:
2008 58th Electronic Components and Technology Conference.
Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial
Autor:
James D. Meindl, D.C. Sekar
Publikováno v:
2007 IEEE International Interconnect Technology Conferencee.
This paper studies the impact of multi-core architectures on design of chip-level interconnect networks. A dual core 3 GHz processor is found to require 23% fewer metal levels than a single core 6 GHz processor while a quad core 1.5 GHz processor nee
Publikováno v:
CICC
An analytical physical model is derived for the first time to predict the first droop power supply noise for non-uniform current switching conditions and arbitrary functional block sizes. The model not only captures the impact of package parameters a
Publikováno v:
2007 Proceedings 57th Electronic Components and Technology Conference.
Compact physical models are derived for predicting power supply noise of chips in the gigascale integration (GSI) era. These models consider both IR-drop and simultaneous switching noise (SSN) and give a quick full waveform description of the first d
Publikováno v:
2006 International Interconnect Technology Conference.
Power consumed by interconnect repeaters is a serious concern for future ICs. Ways to tackle this issue such as unique optimization of repeater and logic transistor technologies, improved repeater insertion methods and 3D integration are discussed. T