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pro vyhledávání: '"D.C. La Tulipe"'
Akademický článek
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Autor:
D.C. La Tulipe, Sampath Purushothaman, Edmund J. Sprogis, R.R. Yu, M. R. Wordeman, Albert M. Young, Narender Rana, Leathen Shi, Steven J. Koester, Kuan-Neng Chen
Publikováno v:
Scopus-Elsevier
An overview of wafer-level three-dimensional (3D)) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3f8be2d0b902d8eee2b863b8788b9867
https://doi.org/10.1147/jrd.2008.5388565
https://doi.org/10.1147/jrd.2008.5388565
Autor:
K. W. Guarini, Arvind Kumar, David J. Frank, Anna W. Topol, Steven E. Steen, A. M. Young, D.C. La Tulipe, G. U. Singco, Meikei Ieong, L. Shi, K. Bernstein
Publikováno v:
IBM Journal of Research and Development. 50:491-506
Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ceea4d757148f5e2d2297fabb9d3492
https://doi.org/10.1147/rd.504.0491
https://doi.org/10.1147/rd.504.0491
Autor:
Barry Linder, E. Cartier, P. Jamison, John C. Arnold, Vijay Narayanan, Evgeni Gusev, Roy A. Carruthers, Vamsi Paruchuri, Kingsuk Maitra, Dianne L. Lacey, Martin M. Frank, D.C. La Tulipe, Michelle L. Steen
Publikováno v:
IEEE Electron Device Letters. 27:591-594
The performance of aggressively scaled (1.4nm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::57f2720785844fe9d4fe865933c74aa5
https://doi.org/10.1109/led.2006.876312
https://doi.org/10.1109/led.2006.876312
Autor:
S.S. Iyer, M. Malley, Alex Hubbard, Deepika Priyadarshini, Kristian Cauffman, Kevin R. Winstel, D.C. La Tulipe, Tuan A. Vo, Spyridon Skordas, Wei Lin, Da Song, S. Kanakasabapathy, Mukta G. Farooq, Robert Hannon, R. Johnson, Seth L. Knupp, A. Upham, Daniel Berger
Publikováno v:
2012 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration.
300mm Si wafer-scale oxide fusion bonding and mechanical/wet etch assisted wafer thinning processes were combined with a TSV-last 3D integration strategy to fabricate electrical open/short yield learning on through-wafer electrical TSV test chains.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca46f723221497b3dc40f5e6d177ea2e
https://doi.org/10.1109/ltb-3d.2012.6238091
https://doi.org/10.1109/ltb-3d.2012.6238091
Publikováno v:
Journal of Crystal Growth. 124:824-828
Undoped surface layers of GaAs and Al0.50Ga0.50As, 50–300 A thick, are shown to improve Schottky diode characteristics on heavily doped GaAs. As the thickness of the undoped GaAs spacer is increased from 0 to 300 A, the reverse leakage current decr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92b92eba7a4df4f9792742ecab044e6f
https://doi.org/10.1016/0022-0248(92)90558-z
https://doi.org/10.1016/0022-0248(92)90558-z
Publikováno v:
Microelectronic Engineering. 17:265-268
In this paper we wish to report on our progress in developing a positive TSI system with emphasis on what we believe is a novel approach for characterizing the silylation process.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b26024c9771c6b5533c3dfd5f381c5d
https://doi.org/10.1016/0167-9317(92)90053-t
https://doi.org/10.1016/0167-9317(92)90053-t
Autor:
Anna W. Topol, J. Patel, D.J. Frnak, Steven E. Steen, D.C. La Tulipe, Jeffrey W. Sleight, L. Ramakrishnan
Publikováno v:
2008 IEEE International SOI Conference.
To address key challenges in transistor scaling [1,2], we have used 3D oxide bonding technology in a new way, to fabricate CMOS devices and circuits in which the gate is on the opposite side of the channel from the contacts between the FET and the fi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2251e59d99e1f8ebca2ef532ea00a380
https://doi.org/10.1109/soi.2008.4656276
https://doi.org/10.1109/soi.2008.4656276
Autor:
H. Baratte, David J. Frank, Thomas N. Jackson, D.C. La Tulipe, Paul M. Solomon, Steven L. Wright
Publikováno v:
IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings..
As-grown (enhancement-mode) and implanted (depletion-mode) GaAs SISFETs are fabricated in selective areas of the same chip with a self-aligned refractory gate process. Both types of devices have comparable characteristics (transconductances of 350mS/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f8c81c1f19244d31773e3deca933e79
https://doi.org/10.1109/cornel.1987.721221
https://doi.org/10.1109/cornel.1987.721221
Publikováno v:
Sixth International Conference Metalorganic Vapor Phase Epitaxy.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d61f6e1b3a7562680cfe1658e3fd203
https://doi.org/10.1109/movpe.1992.664998
https://doi.org/10.1109/movpe.1992.664998