Zobrazeno 1 - 1
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pro vyhledávání: '"D. Zamdmer"'
Autor:
S. Subbanna, Huilong Zhu, T. Shinohara, R.-V. Bentum, H. Kuroda, C. Penny, Jay W. Strane, D. McHerron, D. Harmon, D. Zamdmer, Q. Ye, Yoshiaki Toyoshima, Paul D. Agnello, S. Wu, G. Freeman, L. Tsou, Atsushi Azuma, Scott J. Bukofsky, Carl J. Radens, M. Angyal, M. Fukasawa, Effendi Leobandung, Byeong Y. Kim, M. Gerhardt, Y. Tan, L. Su, Tenko Yamashita, Anda Mocuta, I.C. Inouc, Takeshi Nogami, Scott D. Allen, R. Logan, K. Miyamoto, Shih-Fen Huang, Ravikumar Ramachandran, J. Pellerin, A. Ray, Siddhartha Panda, Christine Norris, H.V. Meer, H. Nayakama, Mizuki Ono, Keith Jenkins, J. Heaps-Nelson, Wenjuan Zhu, D. Ryan, Michael A. Gribelyuk, B. Dirahoui, M. Inohara, E. Nowak, I. Melville, S. Lane, T. Ivers, K. Ida, Scott Halle, Ishtiaq Ahsan, M.-F. Ng, Huicai Zhong, H. Harifuchi, S.-K. Ku, N. Kepler, F. Wirbeleit, Emmanuel F. Crabbe, H. Yan, T. Kawamura, Mahender Kumar, A. Nomura, L. K. Wang, F. Sugaya, H. Hichri, Gary B. Bronner, P. O'Neil, K. Miyashita, Michael P. Belyansky, J. Cheng, S.-H. Rhee, Lars W. Liebmann, D. Yoneyama, Dan Mocuta, K. McStay, G. Sudo, Dureseti Chidambarrao
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL en