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pro vyhledávání: '"D. Wristers"'
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Publikováno v:
Microelectronic Engineering. 28:89-96
This paper reviews recent developments in N 2 O- and NO-based oxynitride gate dielectrics for CMOS ULSI applications. These dielectrics are extremely attractive due to their process simplicity, thickness controllability, and excellent electrical char
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ceb7e8bc11bc5e74cb5f47f9cce4bd7
https://doi.org/10.1016/0167-9317(95)00022-z
https://doi.org/10.1016/0167-9317(95)00022-z
Publikováno v:
Applied Physics Letters. 68:2094-2096
In this letter, we report on the impact of the suppression of boron diffusion via nitridation of SiO2 on gate oxide integrity and device reliability. SiO2 subjected to rapid thermal nitridation in pure nitric oxide (NO) is used to fabricate thin oxyn
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c46648617c4965c0e3ad63e17d3322e8
https://doi.org/10.1063/1.115595
https://doi.org/10.1063/1.115595
Autor:
H.S. Lin, D.Y. Wu, T.J. Chen, C.K. Yang, T.F. Chen, S.W. Sun, L.W. Cheng, P. Fisher, D. Wristers, G. Li, J. Cheek, D. Wu, J.K. Chen, S.C. Chien, M. Michael, C.S. Liang, T.C. Chang
Publikováno v:
Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).
45 nm gate length bulk/PD (partially depleted) SOI transistors, with high performance and ultra-low gate leakage, are presented in this paper. The nFETs and pFETs, operating at Vdd=1.2 V, possess driving currents of 1050 /spl mu/A//spl mu/m and 450 /
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22ea147921f7a4f9c2715b2a0b197a12
https://doi.org/10.1109/essderc.2003.1256902
https://doi.org/10.1109/essderc.2003.1256902
Autor:
Dim-Lee Kwong, Dimitri A. Antoniadis, D. Wristers, A. Ramirez, Andrew P. Ritenour, J. Liu, N. Lu, L. Lee, W.P. Bai
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
In this paper, we report for the first time Ge MOS characteristics with ultra thin rapid thermal CVD HfO/sub 2/ gate dielectrics and TaN gate electrode. Using the newly developed pre-gate cleaning and NH/sub 3/-based Ge surface passivation, the TaN/H
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a44643fb6b86ff15a37dd7be8f1d8ad
https://doi.org/10.1109/vlsit.2003.1221115
https://doi.org/10.1109/vlsit.2003.1221115
Publikováno v:
IEEE Electron Device Letters. 16:319-321
In this paper, we demonstrate the superior diffusion barrier properties of NO-nitrided SiO/sub 2/ in suppressing boron penetration for p/sup +/-polysilicon gated MOS devices. Boron penetration effects have been studied in terms of flatband voltage sh
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c3683ed3e48aa102576c7d59880e8df2
https://doi.org/10.1109/55.388720
https://doi.org/10.1109/55.388720
Autor:
D. Dyer, D. Wristers, P. Ingersoll, Karl Wimmer, R. Stout, John R. Alvis, Yongjoo Jeon, P. Grudowski, J. Conner, D. Bonser, P. Abramowitz, T.V. Gompel, J. Pellerin, J.J. Lee, A. Duvallet, M. Foisy, K. Hellig, S. Lim, D. Hall, L. Vishnubhotla, S. Parihar, A. Nghiem, G.C.-F. Yeap, Kyle Patterson, W. Qi, M. Rendon, Yang Du, Y. Shiho, J. Chen, S. Jallepalli, Marilyn Irene Wright, K. Weidemann, M. Woo, David Burnett, T. Luo, Craig S. Lage, R. Singh, C. Reddy, M. Hall, H.-H. Tseng, S. Veeraraghavan, N. Benavides, N. Ramani
Publikováno v:
Scopus-Elsevier
We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design (M. Fukuma et al., VLSI Tech., 2000) techniques (e.g. well biasing and power down/reduction)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0a237a9f8ada06ab05722eb1c2d43b26
https://doi.org/10.1109/vlsit.2002.1015370
https://doi.org/10.1109/vlsit.2002.1015370
Autor:
M. Celik, G.C.-F. Yeap, Byoung W. Min, Ruigang Li, D. Wristers, Yongjoo Jeon, M. Pelella, D. Wu, S. Krishnan, Wen-Jie Qi, M. Mendicino, G. Burbach, O. Karlsson, A. Wei, M. Fuselier, N. Cave, P. Abramowitz, M. Woo, Ping Yeh, B. Taylor, B. En, J. Conner
Publikováno v:
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
In this report, a high performance silicon-on-insulator (SOI) transistor for the 100 nm CMOS technology node is presented. Partially depleted (PD) transistors were fabricated in a 1000 /spl Aring/-thick silicon film with gate lengths down to 45 nm, u
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3fdb30b7e52a676c77e60d4bac0a3b2
https://doi.org/10.1109/vlsit.2002.1015435
https://doi.org/10.1109/vlsit.2002.1015435
Publikováno v:
Proceedings of 11th International Conference on Ion Implantation Technology.
Using MeV ion implantation and Cz bulk wafer denuding/gettering techniques, we have successfully demonstrated in bulk (non-epi) wafers superior latch-up performance and equivalent surface silicon quality (gate oxide integrity and junction leakage cur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e73bf210ef6bb27d1fae9bf4f068084a
https://doi.org/10.1109/iit.1996.586102
https://doi.org/10.1109/iit.1996.586102
Publikováno v:
Proceedings of 11th International Conference on Ion Implantation Technology.
An integrated P-buried layer formed by MeV ion implantation combined with a localized P-connecting layer has been studied for latch-up isolation improvement for advanced CMOS technology. Latch-up trigger currents have been characterized with regards
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1efbcf81603f7cc1ecafb9581edff22c
https://doi.org/10.1109/iit.1996.586580
https://doi.org/10.1109/iit.1996.586580