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Autor:
R. Divakaruni, Stephan Kudelka, A. Strong, D. Lea, M. Seitz, Scott J. Bukofsky, H. Tews, Juergen Preuninger, D. Tibbel, Jai-Hoon Sim, L. Nesbit, Larry Clevenger, Carl J. Radens, Gary B. Bronner, J. Mandelman, Scott Halle, Gerhard Kunkel, N. Arnold, D. Casarotto, R. Malik, U. Gruening
Publikováno v:
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).
A 0.135 /spl mu/m/sup 2/ trench-capacitor DRAM cell with a trench-sidewall vertical-channel array device has been fabricated using 150 nm groundrules and optical lithography. This 6F/sup 2/ cell features a novel active area layout, a trench-top-oxide