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Autor:
D. Morency, M. Bus, Robert E. Busch, J. Kosson, R. Newhart, J. Morrish, R. Parent, T. Redman, M. Clinton, D. Plouffe, C. Kilmer, E. Thoma, D. Tewarson, T. Bronson
Publikováno v:
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
A 4Mb CMOS DRAM organized 1Mb×4, measuring 6.35mm × 12.3mm, and operating at a typical row access time of 65ns, will be described. The design utilizes a double buffer architecture to achieve a static column access time of 25ns. Half V dd -folded bi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34551c2e1d4311705321fc3fa67419bc
https://doi.org/10.1109/isscc.1987.1157207
https://doi.org/10.1109/isscc.1987.1157207
