Performance Analysis of a Half Bridge Cell Based Asymmetrical Multilevel Inverter Topology with Minimum Components

Autor: Tomei Francesco, Elfaki Imadeldin, Q. Froes Thamires, Ding Yijie, Saeedian Moghadam Ebrahim, Mir Rashid, Amini Mohsen, M. Damato Felice, Tomei Gianfranco, Zhuang Zichong, Javid Jamsheed, Huang Baohua, Sacco Carmina, Ricci Pasquale, Chen Qian, Khullar Naina, Mario di Luca Natale, Kim Chol-Ho, Banu Shaheena, Samin Khan Ghufrana, Chahal S. M. S., Caciari Tiziana, Casale Teodorico, Asif Hanif Muhammad, Wu Hongjie, D. Roy Abeera, Massoni Francesco, Chandrahasan Umayal, S. Castilho Marcelo, Chen Feng, Rashid Umer, G. Patil Asmita, Marchione Stefania, Yun Un-Hui, Ri Kum-Chol, Ricci Lidia, Ke Donghua, Patil Shailendra, Tang Jijun, Kim Chol-Jin, Anzelmo Vincenza, k Jha Chandan, V. Rosati Maria, Ghafary Shahrzad, Zhong Jingpeng, Nardone Nadia, Zhang Jinjin, Massimi Roberto, L. Baldini Regina, Giubilati Roberto, Nadeem Farwa, Li Hyon-Gwang, Ricci Serafino, Lu Yujing, Li Wenbin, Rehman Suriya, Guo Xiaoyi, Vajda Sandor, Zhou Jinlin, K. Mahapatra Debarshi, Muhammad Ikram Mirza, Choe Sunll, Pimpinella Bendetta, Lorusso Giovanna

Publikováno v: Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering). 13:531-545

Background: In Multilevel Inverters (MLI) as the number of level increases, there is a proportionate increase in the count of the semiconductor devices that are employed. Methods: This paper deals with an asymmetrical cascaded H-bridge inverter topol

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https://doi.org/10.2174/2352096512666190417122807