Zobrazeno 1 - 10
of 69
pro vyhledávání: '"D. Restaino"'
Autor:
Todd B. Abrams, Mayrita Arrandale, Chandar Palamadai, Alexander Parker, Nicole Hurst, Shawn Macnish, Darryl D. Restaino
Publikováno v:
2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
As dimensions shrink with each successive semiconductor technology node, the critical size of defects that can impact yield also shrinks. Monitoring the health of process equipment rigorously and regularly for key sources of contamination must be per
Autor:
Sandra G. Malhotra, Sean P. E. Smith, Lynne Gignac, Shyng-Tsong Chen, Judith M. Rubino, Darryl D. Restaino, David L. Rath, Steffen K. Kaldor, Wei-Tsu Tseng, Mahadevaiyer Krishnan, Eric G. Liniger, Chao-Kun Hu, James R. Lloyd, Robert Rosenberg, Donald F. Canaperi, Soon-Cheon Seo, A. Simon
Publikováno v:
Thin Solid Films. 504:274-278
Electromigration mass flow in Cu damascene lines which were connected to W blocking barrier contacts and were capped with either a CoWP, Ta, Ta/TaN, Pd, SiN x , or SiC x N y H z layer was investigated. Cu lines, fabricated with body centered cubic α
Autor:
H. Oguma, T. Bolom, Y. Oda, S. O. Kim, C. Child, S. Allen, G. Bonilla, R. Schiwon, B. Kim, G. Osborne, B. Sundlof, T. Takewaki, E. Kaltalioglu, A. Grill, Q. Fang, D. Edelstein, H. Aizawa, T. Oki, B. Engel, A. Thomas, G. Ribes, S. Hirooka, G. Biery, K. Fujii, S. Molis, H. Sheng, R. Augur, M. Pallachalil, H. Shobha, D. Restaino, H. Masuda, J. H. Ahn, D. Kioussis, Terry A. Spooner, G. Zhang, L. Clevenger, Chao-Kun Hu, R. Quon, Stephen M. Gates, A. Simon, B. Hamieh, Paulo Ferreira, S. M. Singh, E. T. Ryan, R. Sampson, T. Fryxell, A. Ogino, H. Minda, B. Sapp, Richa Gupta, C. Labelle, T. Nogami, E. Wornyo, E. Shimada, T. Daubenspeck, T. J. Tang, T. Shaw, D. Permana, R. Srivastava
Publikováno v:
Microelectronic Engineering. 92:42-44
A cost effective 28nm CMOS Interconnect technology is presented for 28nm node high performance and low power applications. Full entitlement of ultra low-k (ULK) inter-level dielectric is enabled. Copper wiring levels can be combined up to a total of
Autor:
Ellie Yieh, R. Conti, S. Chandran, D. Restaino, D. Cote, Li-Qun Xia, Francimar Campana, Maria Galiano
Publikováno v:
Journal of The Electrochemical Society. 146:1884-1888
As a premetal dielectric, borophosphosilicate glass (BPSG) has been widely used for device planarization. In order to meet the stringent gap filling requirements as the device evolves toward smaller feature sizes, the current BPSG deposition process
Autor:
Li-Qun Xia, S. Chandran, Maria Galiano, S. Nemani, D. Cote, D. Restaino, D. Többen, Ellie Yieh, S. Pichai, R. Conti
Publikováno v:
Journal of The Electrochemical Society. 146:1181-1185
Undoped silicate glass deposited using the tetraethylorthosilicate (TEOS) and ozone thermal reaction has been selected as one of the candidates for shallow trench isolation applications. As a replacement for existing low pressure or atmospheric press
Autor:
Stefan J. Weber, P Weigand, Roy C. Iggulden, R.F. Schnabel, S. B. Brodsky, Darryl D. Restaino, Lawrence A. Clevenger, E.A Mehter
Publikováno v:
Thin Solid Films. 320:63-66
Today, numerous different PVD techniques are used for the filling of sub micron contacts and vias in ULSI devices. One of the most promising approaches is the Al-reflow process. In this process, voids in vias which form during the PVD deposition of A
Autor:
Lynne Gignac, Judith M. Rubino, Donald F. Canaperi, Shyng-Tsong Chen, Chao-Kun Hu, Darryl D. Restaino, Sean P. E. Smith, Robert Rosenberg, B. Herbst, Soon-Cheon Seo
Publikováno v:
Applied Physics Letters. 84:4986-4988
Electromigration of Cu and diffusion of Co in Cu damascene bamboo-like grain structure lines capped with CoWP have been studied for sample temperatures between 350 and 425 °C. Void growth from the Cu line/W via interface was observed. Bulk-like acti
Publikováno v:
Thin Solid Films. 247:104-111
The “W-Capped Aluminum Damascene Process” forms low-resistance wiring for the IBM/Siemens 64 MB dynamic random access memory (DRAM). Damascene wiring is fabricated by etching a trough in a dielectric, filling the trough with metal, and planarizin
Autor:
Kumar Virwani, B. Sundlof, T. Lee, Griselda Bonilla, S. Liang, Anita Madan, Darryl D. Restaino, C. Child, Steven E. Molis, Errol Todd Ryan, Timothy M. Shaw, Timothy H. Daubenspeck, Gordon C. Osborne, N. Klymko, Z. Sun, Hosadurga Shobha, Dimitri R. Kioussis, Clevenger Leigh Anne H, Alfred Grill, H. Masuda, Augur Roderick A, Roger A. Quon, Stephan A. Cohen, Stephen M. Gates
Publikováno v:
2011 IEEE International Interconnect Technology Conference.
There is an ongoing need in the microelectronics industry to increase circuit density in multilevel back-end-of line (BEOL) interconnects to improve the operating speed and reduce power consumption. One way to maintain capacitance-resistance (RC) per
Autor:
Steffen K. Kaldor, Stephane Laforte, David L. Questad, Wolfgang Sauter, Darryl D. Restaino, Clare Johanna Mccarthy, Jennifer Clark, Jon A. Casey
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
During the bond and assembly process of an organic module, the backside of the chip will be in tensile stress. Vertical cracking through the Silicon chip (as shown in Figure 1) can occur when the strength of the chip is lower than the stress that is