Zobrazeno 1 - 10
of 38
pro vyhledávání: '"D. Ravotto"'
Publikováno v:
Scopus-Elsevier
Within the design arena of modern devices based on cutting-edge processor cores, the availability of effective verification, validation and test methodologies able to work on high-level descriptions of processor cores represents an interesting advant
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fbbbdc438d9c1fb15431574119d38c5e
https://doi.org/10.29292/jics.v5i1.311
https://doi.org/10.29292/jics.v5i1.311
Publikováno v:
IEEE Design & Test of Computers. 26:52-63
Testing communication peripherals in an environment of systems on a chip is particularly challenging. The authors explore two test program generation approaches-one fully automated and one deterministically guided-and propose a novel combination of t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c9ef7aa83f77a77496420842cee50c76
https://doi.org/10.1109/mdt.2009.43
https://doi.org/10.1109/mdt.2009.43
Publikováno v:
The Handbook on Reasoning-Based Intelligent Systems
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::541660d5b1663998c5c24a49cbe19f50
https://doi.org/10.1142/9789814329484_0015
https://doi.org/10.1142/9789814329484_0015
Autor:
Matteo Sonza Reorda, Jaime Velasco Medina, Ernesto Sanchez, Michelangelo Grosso, D. Ravotto, Alberto Tonda, Wilson Javier Pérez Holguín
Publikováno v:
Journal of Electronic Testing
Journal of Electronic Testing, Springer Verlag, 2011, 27 (4), pp.505-516. ⟨10.1007/s10836-011-5219-6⟩
Journal of Electronic Testing, Springer Verlag, 2011, 27 (4), pp.505-516. ⟨10.1007/s10836-011-5219-6⟩
International audience; Today's SoCs are composed of a wide variety of modules, such as microprocessor cores, memories, peripherals, and customized blocks directly related to the targeted application. To effectively perform simulation-based design ve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::258779b430e5ff553211c3406ca8d560
https://hal.archives-ouvertes.fr/hal-02481866
https://hal.archives-ouvertes.fr/hal-02481866
A hardware accelerated framework for the generation of design validation programs for SMT processors
Publikováno v:
DDECS
In this paper, we propose an innovative emulation-based framework for the generation of test programs oriented to SMT microprocessor validation. The two major characteristics of the proposed framework are an effective method to gather information abo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8453e2a6db2221a265eded06b0e884b9
https://doi.org/10.1109/ddecs.2010.5491767
https://doi.org/10.1109/ddecs.2010.5491767
Today's SoCs are composed of a high variety of modules, such as microprocessor cores, memories, peripherals, and customized blocks directly related to the targeted application. Testing a peripheral core embedded in a SoC requires two correlated phase
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::149c180a26d93d90e3586ab479f233e8
http://hdl.handle.net/11583/2364056
http://hdl.handle.net/11583/2364056
Autor:
M. Sonza Reorda, W. J. H. Perez, D. Ravotto, Michelangelo Grosso, Ernesto Sanchez, J. Velasco Medina
Publikováno v:
European Test Symposium
Software-based self-test strategies have been mainly proposed to tackle microprocessor testing issues, but may also be applied to peripheral testing. However, testing highly embedded peripherals (e.g., DMA or Interrupt controllers) is a challenging t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cc6b160d8c79ccda12f05ca618361834
http://hdl.handle.net/11583/2372204
http://hdl.handle.net/11583/2372204
Publikováno v:
SBCCI
As CMOS technology scaled to nanometer regimes (100nm and below) power dissipation and power density have become major design constraints. The power consumed by active devices is converted into heat, which in turn increases the substrate temperature.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d66533a07e0ccee31d3680ca9e5e15c1
http://hdl.handle.net/11583/2375541
http://hdl.handle.net/11583/2375541
Publikováno v:
SBCCI
Within the design arena of modern devices based on cutting-edge processor cores, the availability of effective verification, validation and test methodologies able to work on high-level descriptions of processor cores represents an interesting advant
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9bdf1ddb510bdb66412a3390f7abe69f
https://doi.org/10.1145/1601896.1601964
https://doi.org/10.1145/1601896.1601964
Autor:
Ernesto Sanchez, Giovanni Squillero, Alberto Tonda, D. Ravotto, Stefano Gandini, Walter Ruzzarin
Publikováno v:
the 11th Annual conference
the 11th Annual conference, Jul 2009, Montreal, France. pp.1921, ⟨10.1145/1569901.1570238⟩
GECCO
the 11th Annual conference, Jul 2009, Montreal, France. pp.1921, ⟨10.1145/1569901.1570238⟩
GECCO
International audience; Mobile phones are becoming more and more complex devices, both from the hardware and from the software point of view. Consequently, their various parts are often developed separately. Each sub-system or application may be work
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d1f7f6ea2e1b3cba5fd1a2e661ef5706
https://hal.archives-ouvertes.fr/hal-02481987
https://hal.archives-ouvertes.fr/hal-02481987