Zobrazeno 1 - 10
of 49
pro vyhledávání: '"D. Nagalingam"'
Publikováno v:
2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
Autor:
Naiyun Xu, D. Nagalingam, R. Fransiscus, Siong Luong Ting, Pik Kee Tan, A. C. T. Quah, Htin Kyaw, H. H. W. Thoungh, C. Q. Chen, Yanlin Pan, Krishnanunni Menon, P.T. Ng, S. M. Parab, Hao Tan
Publikováno v:
2021 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
Publikováno v:
2021 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
Autor:
S.Y. Thum, H.H.W. Thoungh, Pik Kee Tan, C. Q. Chen, F. Rivai, D. Nagalingam, T.T. Yu, P.T. Ng, S.J. Moon, Siong Luong Ting, S.P. Neo, Yanlin Pan
Publikováno v:
International Symposium for Testing and Failure Analysis.
Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in ord
Autor:
J. Lam, G.B. Ang, D. Nagalingam, S.P. Neo, Zhihong Mai, Francis Rivai, K. H. Yip, P.T. Ng, C.Q. Chen
Publikováno v:
Microelectronics Reliability. :141-144
As semiconductor technology keeps scaling down, many advanced technology and process were applied in the semiconductor process. Especially for the application of IOT (internet of thing) technology, the low leakage and low power consumption product wa
Autor:
S. P. Neo, J.C. Lam, G. B. Ang, S. L. Ting, C. W. Soo, H. H. Ma, C. Q. Chen, A. C. T. Quah, Z. H. Mai, D. Nagalingam
Publikováno v:
Microelectronics Reliability. :255-260
This paper described a low yield case which resulted in a donut shape failing pattern. It also described a scenario where static fault localization is ineffective and a systematic problem solving approach based on symptoms, induction, hypothesis and
Autor:
Alfred Quah, Zhihong Mai, D. Nagalingam, S. Moon, Jeffrey Lam, S.P. Neo, G.B. Ang, Edy Susanto
Publikováno v:
Microelectronics Reliability. 73:76-91
In this paper, two electroluminescence phenomena, which enabled the static electrical fault localization of subtle back-end-of-line metallization defects using near-infrared photon emission microscopy in the logic circuitry and the memory array, are
Publikováno v:
2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA).
In wafer fabrication, sample preparation is becoming increasingly challenging as IC devices evolve to smaller feature sizes and higher densities. [1] Thus, the task of performing successful failure analysis (FA) is more challenging and difficult. Sam
Publikováno v:
2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA).
Modern SoC design incorporates power management circuits to minimize standby leakages of digital logic circuitry. This isolates the logic blocks from being directly powered by the IC’s pad level power supply and ground. As a result, die level stati
Publikováno v:
Microelectronics Reliability. 108:113629
Modern SoC design incorporates power management circuits to minimize standby leakages of digital logic circuitry. This isolates the logic blocks from being directly powered by the IC's pad level power supply and ground. As a result, die level static