3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for $55\ \mu\mathrm{m}-75\ \mu \mathrm{m}$ Mixed Pitch Interconnections on High Density Laminate

Autor: Thomas A. Wassick, Paul S. Andry, Cyril Cabral, Russell Kastberg, Shidong Li, Mukta G. Farooq, Katsuyuki Sakuma, D. McHerron, Rajalingam Sankeerth

Publikováno v: 2021 IEEE 71st Electronic Components and Technology Conference (ECTC).

In this work, a 3D Die-Stack on Substrate (3D-DSS) bonding process has been developed to demonstrate a 3D die stack that has been joined to a mixed pitch ( $5\ \mu\mathrm{m}\ /\ 75\ \mu \mathrm{m}$ ) high density interconnect laminate. By using the 3

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0c8d33e01175c04db3b25994a694d1ea
https://doi.org/10.1109/ectc32696.2021.00056

Advanced Arsenic Doped Epitaxial Growth for Source Drain Extension Formation in Scaled FinFET Devices

Autor: Shashank Sharma, Balasubramanian S. Pranatharthi Haran, Dechao Guo, Hemanth Jagannathan, Michael Chudzik, Kevin R. Winstel, Donald F. Canaperi, H.-J. Gossmann, Lan Yu, Samuel S. Choi, Shogo Mochizuki, Benjamin Colombeau, S.H. Lin, Abhishek Dube, Schubert S. Chu, J. Boland, F. Chang, Nicolas Loubet, M. Cogorno, D. McHerron, M. Stolfi, Richard A. Conti, Qu Jin, Sanjay Natarajan, Liu Patricia M, Zhenxing Bi, Z. Li

Publikováno v: 2018 IEEE International Electron Devices Meeting (IEDM).

In this paper, we demonstrate a novel Source Drain Extension (SDE) approach to enable NMOS device scaling along with improved performance. For the first time, SDE formation with epitaxially grown As doped Si (Si:As) has been examined and compared to

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::faef8419b35847a0ecbfd3358552dfad
https://doi.org/10.1109/iedm.2018.8614543

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High- $\kappa$/Metal-Gate nFinFETs for High-Performance Logic Applications

Autor: R. J. Miller, J. Faltermeier, Pranita Kulkarni, Bruce B. Doris, Kingsuk Maitra, D. McHerron, N R Klymko, E Leobundung, H. Adhikari, Huiming Bu, Chun-Chen Yeh, Katherine L. Saenger, Vamsi Paruchuri, J. O'Neil, Veeraraghavan S. Basker, Ali Khakifirooz, Theodorus E. Standaert, Hemanth Jagannathan

Publikováno v: IEEE Electron Device Letters. 32:713-715

Strained-silicon-on-insulator (SSOI) undoped-body high-κ /metal-gate n-channel fin-shaped field-effect transistors (nFinFETs) at scaled gate lengths and pitches (i.e.,LGATE ~ 25 nm and a contacted gate pitch of 130 nm) were fabricated using a gate-f

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1a1ed78e22846ada1bac7635a99cdc8e
https://doi.org/10.1109/led.2011.2126556

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Autor: Jeffrey C. Shearer, Philip J. Oldiges, Soon-Cheon Seo, Terry A. Spooner, Matthew E. Colburn, Ravikumar Ramachandran, V. Sardesai, Kang-ill Seo, Dinesh Gupta, Richard G. Southwick, Xiao Sun, S. Stieg, H. Cai, S. Kanakasabaphthy, Vamsi Paruchuri, R. Sampson, Lars W. Liebmann, Walter Kleemeier, Kisik Choi, Deok-Hyung Lee, Christopher Prindle, R. Divakaruni, H. Shang, Abhijeet Paul, T. Gow, D. McHerron, Dechao Guo, Fee Li Lie, J. Nam, Neeraj Tripathi, Ruilong Xie, R. Kambhampati, Muthumanickam Sankarapandian, Balasubramanian S. Pranatharthi Haran, Carol Boye, James H. Stathis, B. Hamieh, John Iacoponi, Christopher J. Waskiewicz, Geum-Jong Bae, Derrick Liu, Sanjay Mehta, Reinaldo A. Vega, Terence B. Hook, Min Gyu Sung, Jay W. Strane, D.I. Bae, Robin Chao, Hoon Kim, F. Nelson, Theodorus E. Standaert, L. Jang, Erin Mclellan, M. Celik, S. Nam, Tae-Chan Kim, C.-C. Yeh, Sean D. Burns, P. Montanini, Charan V. V. S. Surisetty, Raghavasimhan Sreenivasan, Ju-Hwan Jung, B. Lherron, S.-B. Ko, E. Alptekin, Huiming Bu, Injo Ok, Jin Cho, Mukesh Khare, J. G. Hong, Gen Tsutsui, Andreas Scholze, Bomsoo Kim, D. Chanemougame, M. Mottura, M. Weybright, H. Mallela, K. Kim, Hemanth Jagannathan, Chanro Park, J. Jenq, Donald F. Canaperi, Young-Kwan Park, R. Jung, Kangguo Cheng

Publikováno v: 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d4d82166b734af3db83f196d83853ba5
https://doi.org/10.1109/vlsit.2014.6894342

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

Autor: H. Kawasaki, Junli Wang, V. Basker, J. Faltermeier, Pranita Kulkarni, James A. O’Neill, Tenko Yamashita, T. Levin, D. McHerron, H. Adhikari, S. Kanakasabapathy, R. C. Johnson, Huiming Bu, R. J. Miller, Hiroshi Sunamura, Mariko Takayanagi, Yu Zhu, Effendi Leobandung, Atsuro Inada, S. Holmes, Jason E. Cummings, Masami Hane, James J. Demarest, Amit Kumar, Atsushi Yagishita, T. Yamamoto, Bruce B. Doris, Hemanth Jagannathan, Erin Mclellan, Chung Hsun Lin, Matthew E. Colburn, Jeremy A. Wahl, Stefan Schmitz, J. Kuss, Kingsuk Maitra, Lisa F. Edge, Vamsi Paruchuri, Theodorus E. Standaert, R. H. Kim, C.-C. Yeh

Publikováno v: 2010 Symposium on VLSI Technology.

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5afe0dec503f0b360dca5be1318fb10e
https://doi.org/10.1109/vlsit.2010.5556135