High performance bulk planar 20nm CMOS technology for low power mobile applications

Autor: Eduard A. Cartier, X. Chen, Pierre Malinge, L. Kang, T. Watanabe, Michael P. Belyansky, L. Economikos, O. Menut, Vijay Narayanan, C. Reddy, R. Divakaruni, Y.H. Park, Ravi Prakash Srivastava, M. Pallachalil, R. Koshy, Dominic J. Schepis, P. Montanini, Keith Kwong Hon Wong, M. Eller, Park Sejun, A. Ogino, H. Mallela, U. Kwon, T. Shimizu, W. Cote, Jay W. Strane, Srikanth Samavedam, M. Chae, Anurag Mittal, R. Sampson, J. Meiring, R. Joy, Huiling Shang, S. Soss, X. Yang, Keith H. Tabakman, M. Oh, W. Lai, C. Tran, S. Jain, E. Josse, D. Codi, H.V. Meer, B.Y. Kim, Jung-Geun Kim, Jin Bum Kim, C. Goldberg, Henry K. Utomo, J. Ciavatti, Barry Linder, R. Vega, W. Neumueller, J. Muncy, Kyung-hwan Cho, Scott J. Bukofsky, Alvin G. Thomas, Dinesh Koli, Katherina Babich, Bomi Kim, S. Lian, E. Alptekin, Y. Liu, S. H. Rhee, X. Wu, R. Arndt, W.L. Tan, Frederic Lalanne, Nam-Sung Kim, Ravikumar Ramachandran, K.Y. Lee, M.H. Nam, Randy W. Mann, Il-Ryong Kim, Yujun Li, V. Sardesai, Siddarth A. Krishnan, C. Tian, D. Levedakis, Seung-Kwon Kim, Jedon Kim, M. Celik, F. Matsuoka, M. Weybright, J. Sudijono, M. Aminpur, B. Hamieh, Greg Northrop, J.W. Lee

Publikováno v: 2012 Symposium on VLSI Technology (VLSIT).

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared w

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0ec874734f9fcf487e547466890b1297
https://doi.org/10.1109/vlsit.2012.6242495

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