Zobrazeno 1 - 10
of 40
pro vyhledávání: '"D. J. Silversmith"'
Publikováno v:
Journal of The Electrochemical Society. 129:2303-2306
Publikováno v:
Thin Solid Films. 93:413-419
An investigation of the formation of refractory metal (tungsten, molybdenum and tantalum) silicides by reaction of the metal with crystalline and polycrystalline silicon at temperatures above 900°C indicates that WSi2 formation can be inhibited by c
Autor:
D. J. Silversmith, B-Y. Tsaur, John C. C. Fan, Steven R. J. Brueck, D. V. Murphy, T. F. Deutsch
Publikováno v:
Applied Physics Letters. 40:895-898
Spatially resolved (∼1 μm) Raman scattering measurements of the Si optical phonon spectrum have been used to map the stress in silicon‐on‐sapphire device structures. Devices defined by an isolated island etch technique exhibit a stress relaxat
Autor:
Jan H. C. Sedlacek, D. J. Silversmith, R. W. Mountain, J.Y. Tsao, Daniel J. Ehrlich, W.S. Graber
Publikováno v:
IEEE Electron Device Letters. 5:32-35
Laser direct-write Al etching and poly-Si deposition have been adapted to the mask-free alteration of simple gate-array test circuits. Simple test structures on commercial CMOS chips have been reconfigured with no degradation in device or circuit per
Publikováno v:
Journal of Applied Physics. 54:3272-3277
Surface damage in Si substrates created by Ar‐ion milling or by reactive‐ion etching in CF4, CHF3, Cl2, SiCl4, or SiF4 has been investigated. Metal‐oxide‐semiconductor capacitors were fabricated on the etched Si substrates, and the interface
Publikováno v:
Journal of The Electrochemical Society. 130:1178-1183
Presentation de modeles pour la formation et l'entrainement de sous-joints et de joints de grains. L'entrainement des sous-joints demande le controle du gradient de temperature, la modulation des contours isothermes et l'orientation cristallographiqu
Autor:
Bor-Yeu Tsaur, John C. C. Fan, D. J. Silversmith, Michael W. Geis, Henry I. Smith, R. W. Mountain
Publikováno v:
Journal of The Electrochemical Society. 129:2812-2818
Autor:
Bor-Yeu Tsaur, Michael W. Geis, R. W. Mountain, John C. C. Fan, R. L. Chapman, D. J. Silversmith
Publikováno v:
IEEE Electron Device Letters. 3:398-401
A CMOS test circuit chip containing six arrays of 360 to 533 parallel transistors, two 31-stage ring oscillators, and two inverter chains has been designed for evaluating SOI wafers prepared by using the graphite strip-heater technique for zone-melti
Publikováno v:
Journal of Applied Physics. 52:5243-5246
Shallow PtSi‐Si Schottky barrier contacts have been formed by heat treatment at 400–500 °C of structures prepared by vacuum deposition of thin alternating Pt and Si layers on n‐type (100) Si substrates. This multilayer technique permits the fo
Publikováno v:
IEEE Electron Device Letters. 3:79-82
The transport properties of zone-melting-recrystallized Si films on SiO 2 -coated Si substrates have been studied by the fabrication and characterization of thin-film resistors and n-channel MOSFET's. Subgrain boundaries, which are the predominant cr