Zobrazeno 1 - 10
of 22
pro vyhledávání: '"D. Ingerly"'
Autor:
Mahjabin Maksud, Hannes Greve, Daniel Pantuso, Chetan Prasad, K. W. Park, Benjamin J. Orr, Peng Bai, I-chen Ho, Steven R. Novak, Zhizheng Zhang, D. Ingerly, Michael P. O'Day, Cheyun Lin, Enamul Kabir, Emre Armagan, Sunny Chugh, Patrick N. Stover, Lance C. Hibbeler, A. Schmitz, Hsinwei Wu
Publikováno v:
IRPS
This work presents silicon reliability characterization of Intel’s Foveros three-dimensional (3D) logic-on-logic stacking technology implemented on the 22FFL process node. Simulations and data demonstrate mechanical strain safe zones around Through
Autor:
Raghavan Kumar, Surya Prekke, D. Ingerly, Nasirul I. Chowdhury, Gomes Wilfred, Ajay Balankutty, Noam Dolev, Martin G. Dixon, Patrick N. Stover, Biswajit Patra, Frank O'Mahony, Pavel V. Rott, Sanjeev Khushu, Lei Jiang
Publikováno v:
ISSCC
The Lakefield processor combines heterogeneous 3D die stacking also called Foveros, with hybrid computing to enable a new class of small form factor mobile products. The stacked die and implementation of the 3D package with PoP memory is shown in Fig
Autor:
H. Ma, G.-S. Kim, Daniel Pantuso, L. Aryasomayajula, D. Borst, R. Criss, S. Amin, P. Sinha, K. C. Kolluru, Patrick N. Stover, D. Ingerly, David Jones, K. Cheemalapati, C. S. Cook, K. Enamul, A. M. Pillai, Z. Zell, A. Sairam, A. Kandas, Prabhanshu Shekhar, Gomes Wilfred, Aparna Telang, C.F. Petersburg, M. Phen-givoni, Ajay Balankutty, A. Chandra
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
This paper presents the key silicon features of Intel’s 3D stacking technology, Foveros, as it is used to enable logic-on-logic die stacking. A robust face-to-face die connection is enabled with a high yielding, robust microbump connection. Additio
Autor:
Patel Reken, P. Yashar, C. Pelto, I. Tsameret, C. Petersburg, J. Longun, I. Jin, D. Ingerly, L. Rockford, Hsiao-Kang Chang, Conor P. Puls, P. Plekhanov, Muhammet Uncuer, Kevin J. Fischer, H. Kilambi
Publikováno v:
2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).
We describe here performance enhancement to Intel's 14nm high-performance logic technology interconnects and back end stack and introduce the SOC technology family of interconnects. Enhancement includes improved RC performance and intrinsic capacitan
Autor:
J. Lee, P. Bai, T. Leo, S. K.-Y. Shi, P. Vandervoorn, D. Ingerly, L. Rockford, Ramaswamy Rahul, Y.-W. Chen, Nidhi Nidhi, F. Al-Amoody, M. Jang, K. Byon, T. Rana, Curtis Tsai, A. Zainuddin, C. Quincy, Eric Karl, L. Yang, Hafez Walid M, Chetan Prasad, C. Petersburg, Olac-Vaw Roman W, K. Komeyli, A. Kumar, Chang Hsu-Yu, Anand Subramaniam, N. L. Dias, Tsung-Yuan Chang, H. Kilambi, K. Phoa, Pei-Chi Liu, Chen-Guan Lee, C.-H. Jan
Publikováno v:
VLSIC
A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the
Publikováno v:
Journal of Electronic Materials. 31:1330-1336
PdAl was selected as a reactive contact to n-(In0.52Al0.48)As with the intention of forming a thin, AlAs-enriched interlayer of graded (In1−xAlx)As semiconductor alloy, following rapid thermal annealing. Selection of PdAl was based on the experimen
Autor:
Christopher D. Thomas, Michael L. Hattendorf, Mark R. Brazier, K. Zawadzki, R. McFadden, P. Hentges, J. Seiple, W. Han, D. Ingerly, S. Jaloviar, Cory E. Weber, Huichu Liu, Robert James, C. Auth, C. Parker, Kaizad Mistry, M. Prince, V. Chikarmane, S. Ramey, J. Neirynck, A. Blattner, J. Roesler, M. Bost, P. Yashar, D. Hanken, J. Jopling, Ian R. Post, B. McIntyre, C. Kenyon, T. Troeger, S. Pradhan, Pulkit Jain, D. Towner, C. Allen, David Jones, J. Hicks, Timothy E. Glassman, J. Sandford, L. Pipes, R. Heussner, T. Reynolds, M. Buehler, Daniel B. Bergstrom, Tahir Ghani, Pete Smith, R. Grover, Subhash M. Joshi
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resultin
Autor:
C. Ege, A. Agrawal, A. Schmitz, A. Kandas, T. Mule, M. Buehler, D. Rao, J. Hicks, P. Parthangal, David Jones, P. Yashar, R. McFadden, Kaizad Mistry, R. Ascazubi, V. Chikarmane, K. S. Lee, N. Speer, J. Roesler, C. Ganpule, Guotao Wang, D. Ingerly, Timothy E. Glassman, R. Grover, A. Blattner, Y. Shusterman, Manvi Sharma, H. Khan, A. Madhavan, N. Lazo, P. Tiwari, P. Hentges, J. Shin, D. Parsons, Sudarshan Rangaraj, H. Liu, B. Choudhury, F. Cinnor
Publikováno v:
2012 IEEE International Interconnect Technology Conference.
We describe interconnect features for Intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects. Metal-1 through Metal-6 feature a new ultra-low-k carbon doped oxide (CDO) and a low-k etch
Autor:
K. Lee, S. Haight, P. Yashar, S. Williams, P. Moon, H. Liu, R. Grover, S. Sattiraju, S. Agraharam, D. Becher, M. Goodner, S. Nolen, P. Ramanarayanan, K. Fischer, N. Patel, D. Ingerly, T. Ibrahim, T. Mule, T. Schroeder, E. Mays, S. Pradhan, C. Litteken, H. Kothari, Jun He, V. Chikarmane, S. Joshi, Y. Lin, J. Robinson
Publikováno v:
2008 International Interconnect Technology Conference.
Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal
Autor:
D. Ingerly, K. Zawadzki, R. James, C. Allen, Kaizad Mistry, B. Beattie, W. Han, Lucian Shifren, J. Sebastian, M. Bost, C. Kenyon, Pete Smith, D. Simon, D. Hanken, G. Ding, J. Maiz, C. Thomas, L. Pipes, Annalisa Cappellani, Pulkit Jain, J. He, M. Hattendorf, T. Troeger, Subhash M. Joshi, R. Chau, L. Jong, D. Parsons, Daniel B. Bergstrom, B. Mclntyre, Tahir Ghani, T. Reynolds, Swaminathan Sivakumar, J. Hicks, S. Williams, C. H. Choi, K. Kuhn, C. Auth, Pushkar Ranade, K. Fischer, M. Buehler, M. Brazier, M. Prince, J. Seiple, Chetan Prasad, J. Neirynck, P. Vandervoorn, Huichu Liu, J. Sandford, S. Pae, R. Huessner, K. Lee, C. Parker, P. Moon, R. Grover
Publikováno v:
2007 IEEE International Electron Devices Meeting.
A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and