Výsledky vyhledávání - "D. H. van Dorp"

Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation

Autor: Guillaume Boccardi, Hiroaki Arimura, Roger Loo, Samuel Suhard, Daire J. Cott, Thierry Conard, Naoto Horiguchi, L.-A. Ragnarsson, V. De Heyn, Jerome Mitard, Dan Mocuta, Liesbeth Witters, H. Dekkers, D. H. van Dorp, Nadine Collaert, Kurt Wostyn

Publikováno v: IEEE Transactions on Electron Devices. 66:5387-5392

This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high- ${k}$ last process. SiO2 dummy gate oxide (D

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1dd5f23cc243b67badeb99d80e2e88e1
https://doi.org/10.1109/ted.2019.2950332

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A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation

Publikováno v: 2019 Symposium on VLSI Technology.

We have demonstrated Ge nFinFETs with a record high $\text{G}_{\text{mSA}\Gamma}/\text{SS}_{\text{SAT}}$ and PBTI reliability by improving the RMG high-k last process. The SiO 2 dummy gate oxide (DGO) deposition and removal processes have been identi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::372d860fefbeb4848dc647da0126fe8d
https://doi.org/10.23919/vlsit.2019.8776535

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Anodic Etching of n-GaN Epilayer into Porous GaN and Its Photoelectrochemical Properties

Autor: Philippe M. Vereecken, Gustaaf Borghs, Wei-Jhih Tseng, D. H. van Dorp, Ruben Lieten

Publikováno v: The Journal of Physical Chemistry C. 118:29492-29498

Porous n-GaN has been fabricated using electrochemical anodic etching in a 0.5 M H2SO4 solution in the dark for different biases (5.5–18.0 V). The pore morphology of the porous GaN shows distinctive differences: from narrow branching pores to wide

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::94959f483c9acc0ecac2af58975cbd66
https://doi.org/10.1021/jp508314q

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Impact of Plasma-Induced Surface Damage on the Photoelectrochemical Properties of GaN Pillars Fabricated by Dry Etching

Autor: D. H. van Dorp, Gustaaf Borghs, Wei-Jhih Tseng, R. Langer, Ruben Lieten, Philippe M. Vereecken

Publikováno v: The Journal of Physical Chemistry C. 118:11261-11266

n-GaN pillar photoanodes are fabricated by dry etching of a planar GaN epilayer. The increased surface area results in a plateau photocurrent enhancement of 84%. However, surface damage is introduced during dry etching. In this work, the surface dama

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6a44249d961ded2c73be68be381251a3
https://doi.org/10.1021/jp503119n

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Light-Induced Electrochemical Deposition of Ni for Si Solar Cell Processing

Autor: D. H. van Dorp, Loic Tous, Richard Russell, J. Sniekers, Harold Philipsen, Jozef Szlufcik, G. Bonneux

Publikováno v: ECS Solid State Letters. 3:P45-P48

This work outlines the general electrochemical features of the Ni light-induced deposition process. Typical observations for the deposition on textured solar cells are discussed and compared to planar n-Si (100) electrodes. The electrochemical measur

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8614a3429b00a1997e5d3199e2acb167
https://doi.org/10.1149/2.006404ssl

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Etching of III-V Materials Determined by ICP-MS with Sub-Nanometer Precision

Autor: D. H. van Dorp, Daniel Cuypers, Sophia Arnauts, S. De Gendt, Frank Holsteyns, Jens Rip

Publikováno v: ECS Journal of Solid State Science and Technology. 3:N3064-N3068

The use of inductively coupled plasma mass spectrometry (ICP-MS) is proposed in order to study the etching of III-V substrates at the sub nanometer level in diluted chemistries containing hydrochloric (HCl) or sulfuric acid (H2SO4). Based on the stab

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a5bd949a9eaa1f911caf9697638532aa
https://doi.org/10.1149/2.012401jss

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Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm

Publikováno v: 2016 IEEE Symposium on VLSI Technology.

We report In 0.53 GaAs-channel gate-all-around FETs with channel width down to 7nm and L g down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalabili

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7946494be7347544afb35cbd10fc59d0
https://doi.org/10.1109/vlsit.2016.7573420

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