Zobrazeno 1 - 10
of 65
pro vyhledávání: '"D. Greenlaw"'
Autor:
D. Greenlaw, Jon D. Cheek, Manfred Horstmann, Christoph Schwan, Markus Lenski, Peter Huebler, Scott Luning, R. van Bentum, N. Kepler, Matthias Schaller, James F. Buller, Hartmut Ruelke, Kai Frohberg, Gert Burbach, Rolf Stephan, J. Klais, S. Krishnan, Jörg Hohage, Andy Wei, Th. Feudel, Michael Raab, G. Grasshoff, Karsten Wieczorek, Martin Gerhardt
Publikováno v:
Materials Science and Engineering: B. :3-8
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI t
Autor:
Manfred Horstmann, D. Greenlaw, Th. Feudel, M. Herden, Ch. Krueger, Lutz Herrmann, Martin Gerhardt, Daniel Gehre, Michael Raab
Publikováno v:
Materials Science in Semiconductor Processing. 7:369-374
It is commonly assumed that reducing the source–drain extension (SDE) junction depth is a key element for next-generation technology nodes. This can either be achieved by reducing the implantation energy or by reducing the thermal budget of the ann
Publikováno v:
Quality Assurance. 8:181-187
The quality evaluation and assessment of radiological data is the final step in the overall environmental data decisionprocess. This quality evaluation and assessment process is performed outside of the laboratory, and generally the radiochemist is n
Autor:
M. Majer, Maciej Wiatr, S. J. Wong, Casey Scott, V. Shah, D. Greenlaw, Rolf Geilenkeuser, T. Rodes, Karsten Wieczorek, Tilo Mantei, Richard Heller, Manfred Horstmann, E. Pruefer, Jan Hoentschel
Publikováno v:
2009 IEEE International Reliability Physics Symposium.
The impact of HCI and NBTI on device DC, Ring Oscillator (RO) AC as well as on the degradation of product operating frequency (F MAX ) has been extensively studied. We have developed a method, which allows the compensation of HCI/NBTI-related device
Autor:
Michael Raab, W. Klix, Thorsten Kammler, D. Greenlaw, Andreas Gehring, Jan Hoentschel, S. Muehle, Tom Herrmann, Manfred Horstmann, Andre Poock, Thilo Scheiper, T. Lingner, Christian Krueger, P. Shi, Rolf Stephan, R. Stenzel, Thomas Feudel, P. Huebler, Maciej Wiatr, Andy Wei, Robert Mulfinger
Publikováno v:
2008 IEEE International Electron Devices Meeting.
Sub-40 nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65 nm and 45 nm PD-SOI CMOS technologies. With optimization, the asymmetric NMOS and PMOS saturation drive currents improve up to 12% and 10
Autor:
Peter Javorka, Casey Scott, D. Greenlaw, Andreas Gehring, B. Mulfinger, Markus Lenski, H. Geisler, Anthony Mowry, T. Mantei, Guido Koerner, Manfred Horstmann, Maciej Wiatr, Katja Huy, Roman Boschke, J. Klais, Ralf Otterbach, Andy Wei
Publikováno v:
2007 International Semiconductor Device Research Symposium.
Stress engineering has become the sine qua non of any advanced CMOS technology since the 90nm technology node. In this paper, we focus on the influence of material properties and anneal sequences on the benefit of the stress-memorization technique fo
Autor:
Markus Lenski, Kai Frohberg, Maciej Wiatr, D. Greenlaw, Andreas Gehring, Andy Wei, Manfred Horstmann, Peter Javorka, Thorsten Kammler, Roman Boschke, Anthony Mowry, Thomas Feudel, Ralf Richter
Publikováno v:
2007 15th International Conference on Advanced Thermal Processing of Semiconductors.
We have extensively studied stress enhancing techniques to increase channel mobility starting at the 130 nm technology node and continued this towards the 45 nm node. Stressed overlayers and spacer materials, strained SOI substrates, embedded SiGe an
Autor:
Manfred Horstmann, Casey Scott, Maciej Wiatr, Anthony Mowry, Frank Wirbeleit, R. Callahan, S. Duenkel, Roman Boschke, Ralf Otterbach, Guido Koerner, D. Greenlaw, Andreas Gehring, Michael Raab, N. Krumm, Andy Wei, Martin Gerhardt, Thomas Feudel, Markus Lenski, Jan Hoentschel
Publikováno v:
2007 IEEE Symposium on VLSI Technology.
Two distinct stress memorization phenomena in advanced SOI CMOS are reported in this work. Both require a capping layer and anneal, but can be categorized as techniques 1) requiring an amorphized source/drain region and low temperature anneal, and 2)
Autor:
Th. Feudel, J. Kluth, Lutz Herrmann, P. Fisher, Manfred Horstmann, D. Greenlaw, Martin Gerhardt, M. Herden
Publikováno v:
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors.
With the need to reduce vertical and lateral device dimensions, submelt Laser and flash anneal either with or without prior spike rapid thermal anneal (sRTA) has recently attracted attention. It combines improved active area activation with reduced g
Autor:
John A. Fitzsimmons, Vincent J. McGahay, K. Malone, M. Minami, Siddhartha Panda, Manfred Horstmann, A. Wei, Helmut Bierstedt, H. Nii, A. Waite, A. Sakamoto, Michael A. Gribelyuk, M. Cullinan-Scholl, D. Harmon, A. Hellmich, M. Kiene, Patrick Press, Hartmut Ruelke, H. Zhu, H. Chen, H. Nakayama, Anthony G. Domenicucci, G. Sudo, Henry A. Nye, P. Fisher, Hans-Jürgen Engelmann, H. VanMeer, M. Newport, X. Chen, Tenko Yamashita, Cathryn Christiansen, Hasan M. Nayfeh, Dureseti Chidambarrao, Guido Koerner, Christopher D. Muzzy, S.-F. Huang, Ralf Otterbach, David M. Fried, J. Kluth, Jörg Hohage, M. Trentsch, I. Peidous, Thorsten Kammler, Mukesh Khare, Dominic J. Schepis, K. Rim, Spooner Terry A, K. Miyamoto, P.V. McLaughlin, Michael Raab, T. H. Ivers, Dan Mocuta, D.R. Davies, Jason Gill, Scott Luning, Woo-Hyeong Lee, Gary B. Bronner, Judson R. Holt, Gregory G. Freeman, Matthias Schaller, R. Murphy, J. Pellerin, J. Klais, Kai Frohberg, A. Neu, N. Kepler, R. Bolam, C. Labelle, Anuj Madan, K. Hempel, C. Reichel, Heike Salz, J. Hontschel, T. Sato, J. Cheng, D. Greenlaw, Linda Black, Paul D. Agnello, K. Ida
Publikováno v:
Scopus-Elsevier
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a n