Zobrazeno 1 - 10
of 26
pro vyhledávání: '"D. Gogl"'
Autor:
S. M. Alam, D. Houssameddine, F. Neumeyer, I. Rahman, M. DeHerrera, S. Ikegawa, P. Sanchez, X. Zhang, Y. Wang, J. Williams, D. Gogl, H. Xu, M. Farook, D. Aceves, H. K. Lee, F. B. Mancoff, M. Chou, CH. Tan, B. Huang, S. Mukherjee, M. Lu, A. Shah, K. Nagel, Y. Kim, S. Aggarwal
Publikováno v:
2022 IEEE International Memory Workshop (IMW).
Autor:
Michael Kund, Heinz Hoenigschmid, L. Altimime, Ralf Symanczyk, D. Gogl, G. Mueller, Michael Markert, Corvin Liaw, S. Bournat, Stefan Dietrich, Michael Angerbauer, Milena Ivanov
Publikováno v:
IEEE Journal of Solid-State Circuits. 42:839-845
A 2-Mbit CBRAM (Conductive Bridging Random Access Memory) core has been developed utilizing a 90 nm, VDD=1.5 V process technology. The presented design uses an 8F2 (0.0648 mum2) 1T1CBJ (1-Transistor/1-Conductive Bridging Junction) cell and introduces
Autor:
E. Gow, K. Maloney, Andre Sturm, Malissa J. Wood, J. DeBrosse, W. Obermeyer, C. Barwin, William J. Gallagher, Heinz Hoenigschmid, Gerhard Mueller, A.R. Sitaram, D. Willmott, Stefan Lammers, Hans-Heinrich Viehmann, Thomas M. Maffitt, C. Arndt, D. Gogl, Mark C. H. Lamorey, Yu Lu, A. Bette
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:902-908
A 16-Mb magnetic random access memory (MRAM) is demonstrated in 0.18-/spl mu/m three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42/spl mu/m/sup 2/ 1-transistor 1-magnetic tun
Autor:
Stefan Lammers, Gerhard Müller, R. P. Robertazzi, W. Obermaier, William J. Gallagher, William Robert Reohr, Hans-Heinrich Viehmann, Daniel Braun, C. Arndt, D. Gogl, J. DeBrosse, A. Bette, Heinz Hoenigschmid, R.P. Havreluk, D. Casarotto
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:678-683
A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transisto
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:1387-1395
A 1-Kbit high-temperature EEPROM memory module has been developed in a 1.6-/spl mu/m thin-film SIMOX technology. The memory array is based on single-poly EEPROM cells, which are erased and programmed by Fowler-Nordheim tunneling. Operation at elevate
Autor:
X. Zhang, N. D. Rizzo, D. Gogl, Jon M. Slaughter, Thomas W. Andre, J. Janesky, Dimitri Houssameddine, Syed M. Alam, W. Meadows, Chitra K. Subramanian, H. Lin
Publikováno v:
CICC
Magnetoresistive Random Access Memory (MRAM) technology emerged from research and development into volume production within the last decade in the form of Toggle MRAM. The latest Magnetic Tunnel Junction (MTJ) based memory technology, Spin-Torque MRA
Autor:
Heinz Hönigschmid, L. Altimime, Michael Angerbauer, D. Gogl, G. M¿ller, M. Markert, Corvin Liaw, Milena Dimitrova, S. Bournat, R. Symanczyk, S. Dietrich
Publikováno v:
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..
A 2Mbit CBRAM (conductive bridging random access memory) core has been developed utilizing a 90nm, VDD = 1.5V process technology. The presented design uses an 8F2 (0.0648mum2) 1T1CBJ (1-transistor/1-conductive bridging junction) cell and introduces a
Autor:
Rok Dittrich, A. Bette, P. Beer, G. Muller, J. Schmid, S. Bournat, L. Altimime, S. Lammers, H. Honigschmid, D. Gogl, R. Gardic
Publikováno v:
ISSCC
As MRAM technology is maturing, the need for developing a strategy to identify and replace marginal bits during read/write operation becomes necessary. The methodology and circuit techniques for read/write signal-margin screening implemented in a 0.1
Publikováno v:
IEEE Electron Device Letters. 18:541-543
A thin-film SIMOX technology has been used for fabrication of a single-polysilicon EEPROM cell suitable for high-temperature applications. The two transistor cell is composed of a select transistor and a floating gate transistor with 10 nm tunnel oxi
Publikováno v:
1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4).
This work presents an easy-to-implement and fast lumped-element circuit model for the parasitics of complex low-loss surface acoustic wave (SAW) devices such as interdigitated interdigital transducer (IIDT) and image impedance connected (IIC) filters