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pro vyhledávání: '"D. Etiemble"'
Akademický článek
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Autor:
D. Etiemble, L. Lacassagne
Publikováno v:
International Conference on Parallel Processing, 2004. ICPP 2004..
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::899aa99359026e5212e24b487197bfb4
https://doi.org/10.1109/icpp.2004.1327964
https://doi.org/10.1109/icpp.2004.1327964
Publikováno v:
[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation.
The communication system of a massively parallel architecture called MEGA is presented. The implications of massive parallelism for routing strategies and communication models are discussed. A routing strategy, called forced routing, is proposed. It
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f726ca5db7761373c2d1c5ad698aef59
https://doi.org/10.1109/fmpc.1990.89484
https://doi.org/10.1109/fmpc.1990.89484
Publikováno v:
EUROMICRO
Studying architectural improvements for microprocessors and their memory hierarchies and evaluating the corresponding performance generally need trace driven simulation. Hardware is modeled, benchmark traces are generated and applied to the model and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73223944a33822408f37b72369769ea1
https://doi.org/10.1109/eurmic.1997.617339
https://doi.org/10.1109/eurmic.1997.617339
Publikováno v:
EUROMICRO
We present a methodology to evaluate performance of the memory hierarchy of PC microcomputers. This methodology is based on synthetic bus traces which allow simulation of the memory hierarchy without having to build a model of the microprocessor. As
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6d1f2e736a5a7934d595d5da57dac20c
https://doi.org/10.1109/eurmic.1997.617340
https://doi.org/10.1109/eurmic.1997.617340
Autor:
F. Cappello, D. Etiemble
Publikováno v:
ACM/IEEE SC 2000 Conference (SC'00).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3bf041efee3420dd0b2d2a71c121730e
https://doi.org/10.1109/sc.2000.10001
https://doi.org/10.1109/sc.2000.10001
Publikováno v:
Revue de Physique Appliquée
Revue de Physique Appliquée, Société française de physique / EDP, 1985, 20 (2), pp.71-75. ⟨10.1051/rphysap:0198500200207100⟩
Revue de Physique Appliquée, Société française de physique / EDP, 1985, 20 (2), pp.71-75. ⟨10.1051/rphysap:0198500200207100⟩
L'utilisation de ROMS 4-valuées, avec 2 bits par cellule, est une solution intéressante pour diminuer la taille des mémoires à lecture seule (ROM) de grosse capacité. Alors que la publication originale d'Intel ne donnait aucune information sur l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c0bc316f92ef9d57d7bbac9e96bcb4f7
https://doi.org/10.1051/rphysap:0198500200207100
https://doi.org/10.1051/rphysap:0198500200207100
Autor:
J.P. Aillaud, D. Etiemble
Publikováno v:
Euromicro Newsletter. 6:249-255
Pin limitation has always been an important problem of Integrated Circuits Packages. In this paper, we examine multiple valued logic as an alternative approach to time multiplexing. TTL and CMOS 4-2 and 2–4 interface circuits are presented and it i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::32d05fab7087240d6ea785b6cb32fd60
https://doi.org/10.1016/0303-1268(80)90155-8
https://doi.org/10.1016/0303-1268(80)90155-8
Publikováno v:
21st Design Automation Conference Proceedings.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::04e9cd658e3a5c6cd6c5d5a935bc9761
https://doi.org/10.1109/dac.1984.1585819
https://doi.org/10.1109/dac.1984.1585819
Akademický článek
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