Zobrazeno 1 - 10
of 122
pro vyhledávání: '"D. Batuk"'
Autor:
C. Porret, J.-L. Everaert, M. Schaekers, L.-A. Ragnarsson, A. Hikavyy, E. Rosseel, G. Rengo, R. Loo, R. Khazaka, M. Givens, X. Piao, S. Mertens, N. Heylen, H. Mertens, C. Toledo De Carvalho Cavalcante, G. Sterckx, S. Brus, A. Nalin Mehta, M. Korytov, D. Batuk, P. Favia, R. Langer, G. Pourtois, J. Swerts, E. Dentoni Litta, N. Horiguchi
Publikováno v:
2022 International Electron Devices Meeting (IEDM).
Autor:
H. Mertens, R. Ritzenthaler, Y. Oniki, P. Puttarame Gowda, G. Mannaert, F. Sebaai, A. Hikavyy, E. Rosseel, E. Dupuy, A. Peter, K. Vandersmissen, D. Radisic, B. Briggs, D. Batuk, J. Geypen, G. Martinez-Alanis, F. Seidel, O. Richard, B.T. Chan, J. Mitard, E. Dentoni Litta, N. Horiguchi
Publikováno v:
2022 International Electron Devices Meeting (IEDM).
Autor:
V. Vega-Gonzalez, D. Radisic, S. Choudhury, D. Tierno, A. Thiam, D. Batuk, G.T. Martinez, F. Seidel, S. Decoster, S. Kundu, D. Tsvetanova, A. Peter, H. De Coster, A. Sepulveda-Marquez, E. Altamirano-Sanchez, Bt Chan, Y. Drissi, Y. Sherazi, J. Uk-Lee, I. Ciofi, G. Murdoch, N. Nagesh, G. Hellings, J. Ryckaert, S. Biesemans, E. Dentoni Litta, N. Horiguchi, S. Park, Zs. Tokei
Publikováno v:
2022 International Electron Devices Meeting (IEDM).
Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control
Autor:
S. Subhechha, N. Rassoul, A. Belmonte, H. Hody, H. Dekkers, M. J. van Setten, A. Chasin, S.H. Sharifi, K. Banerjee, H. Puliyalil, S. Kundu, M. Pak, D. Tsvetanova, N. Bazzazian, K. Vandersmissen, D. Batuk, J. Geypen, J. Heijlen, R. Delhougne, G. S. Kar
Publikováno v:
2022 International Conference on IC Design and Technology (ICICDT).
Autor:
A. Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, H. Arimura, M. Stucchi, A. De Keersgieter, M. Hosseini, T. Hopf, K. D'have, S. Wang, E. Dupuy, G. Mannaert, K. Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, T. Schram, B. Briggs, C. Lorant, E. Rosseel, A. Hikavyy, R. Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, K. Devriendt, B. T. Chan, S. Demuynck, G. Hiblot, G. Van der Plas, J. Ryckaert, G. Beyer, E. Dentoni Litta, E. Beyne, N. Horiguchi
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Autor:
S. Subhechha, N. Rassoul, A. Belmonte, H. Hody, H. Dekkers, M. J. van Setten, A. Chasin, S.H. Sharifi, S. Sutar, L. Magnarin, U. Celano, H. Puliyalil, S. Kundu, M. Pak, L. Teugels, D. Tsvetanova, N. Bazzazian, K. Vandersmissen, C. Biasotto, D. Batuk, J. Geypen, J. Heijlen, R. Delhougne, G. S. Kar
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Autor:
A. Belmonte, H. Oh, S. Subhechha, N. Rassoul, H. Hody, H. Dekkers, R. Delhougne, L. Ricotti, K. Banerjee, A. Chasin, M. J. van Setten, H. Puliyalil, M. Pak, L. Teugels, D. Tsvetanova, K. Vandersmissen, S. Kundu, J. Heijlen, D. Batuk, J. Geypen, L. Goux, G. S. Kar
Publikováno v:
2021 IEEE International Electron Devices Meeting (IEDM).
Autor:
Philippe Leray, N. Jourdan, O. Varela Pedreira, E. Dentoni-Litta, Thomas Witters, Werner Gillijns, Nancy Heylen, L. Ramakers, E. Grieten, Zaid El-Mekki, Gayle Murdoch, V. Vega-Gonzalez, Anne-Laure Charley, Ivan Ciofi, Zsolt Tokei, H. Vats, S. V. Gompel, M. H. van der Veen, L. Halipre, J. Swerts, A. Haider, Bilal Chehab, S. Park, N. Bazzazian, Quoc Toan Le, B. De Wachter, T. Peissker, Harinarayanan Puliyalil, Naoto Horiguchi, Miroslav Cupak, J. Versluijs, G. T. Martinez, Y. Kimura, R. Kim, J. Geypen, J. Uk-Lee, N. Nagesh, D. Montero, L. Rynders, M. Ercken, D. Batuk, K. Croes, Patrick Verdonck, Manoj Jaysankar, Y. Drissi, T. Webers
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC).
The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CD bottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison between ruthenium (Ru) and cobalt (Co) chemical vapor deposition (CVD) metallizations. Ru gave a
Autor:
P. Schuddinck, J. Hung, Sylvain Baudot, Yong Kong Siew, D. Batuk, P. Morin, X. Zhou, R. Koret, E. Capogreco, E. Dentoni Litta, S. Subramanian, G. Mannaert, Farid Sebaai, Naoto Horiguchi, Alessio Spessot, Maryamsadat Hosseini, Thomas Chiarella, T. Hopf, D. Radisic, Antony Premkumar Peter, Andriy Hikavyy, G. T. Martinez, Boon Teik Chan, B. Briggs, S. Sarkar, Anabela Veloso, S. Wang, Steven Demuynck, Katia Devriendt, Erik Rosseel, Julien Ryckaert, Juergen Boemmels
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a