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pro vyhledávání: '"D. Bakalis"'
Akademický článek
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Autor:
D. Bakalis, Evangelos Vassalos
Publikováno v:
2019 Panhellenic Conference on Electronics & Telecommunications (PACET).
Even moduli of the $2^{n}-2$ form have been recently proposed in the design of various digital systems that utilize the Residue Number System (RNS), as an alternative to the dominating modulo channel of $2^{n}$ . Although efficient arithmetic units a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f17933961cb457c3bfa53a69377b8a9f
https://doi.org/10.1109/pacet48583.2019.8956249
https://doi.org/10.1109/pacet48583.2019.8956249
Autor:
D. Bakalis, Evangelos Vassalos
Publikováno v:
International Journal of Electronics. 102:2062-2074
Moduli of the 2n and 2n ± 1 forms are usually employed in designs that adopt the residue number system. However, in several cases such as in finite impulse response filters and communication components, a modulo value equal to 2n − 2 can be used.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a2e6d289646242671b120bea99b35915
https://doi.org/10.1080/00207217.2015.1020528
https://doi.org/10.1080/00207217.2015.1020528
Publikováno v:
Circuits, Systems, and Signal Processing. 34:1041-1056
A Hamming distance comparator (also known as $$k$$k-order comparator) compares its two operands and outputs an agreement if they differ in less than $$k$$k corresponding bits. In this paper, we introduce novel architectures for the design of Hamming
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99a4743714e902a3c8f29de294082b82
https://doi.org/10.1007/s00034-014-9891-5
https://doi.org/10.1007/s00034-014-9891-5
Akademický článek
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Autor:
D. Bakalis, Haridimos T. Vergos
Publikováno v:
Microprocessors and Microsystems. 36:409-419
Multi-modulus architectures, that is, architectures that can deal with more than one modulo cases, are very useful for reconfigurable processors and fault-tolerant systems that are based on the residue number system (RNS). Two novel architectures are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6bd9bc40e4d8622cb5d54dc9f5aa671
https://doi.org/10.1016/j.micpro.2012.02.004
https://doi.org/10.1016/j.micpro.2012.02.004
Publikováno v:
Circuits, Systems, and Signal Processing. 30:1445-1461
Novel architectures for designing modulo 2 n +1 subtractors and combined adders/subtractors are proposed in this manuscript. Both the normal and the diminished-one representations of the operands are considered. Unit gate estimates and CMOS VLSI impl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f3881e73255f4f1313f336083d9dcfc
https://doi.org/10.1007/s00034-011-9326-5
https://doi.org/10.1007/s00034-011-9326-5
Publikováno v:
Integration. 44:163-174
Modulo 2^n+/-1 squarers are useful components for designing special purpose digital signal processors that internally use a residue number system and for implementing the modulo exponentiators and multiplicative inverses required in cryptographic alg
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::74142e1feef8f9622d84e677928c711a
https://doi.org/10.1016/j.vlsi.2011.03.006
https://doi.org/10.1016/j.vlsi.2011.03.006
Autor:
D. Bakalis, Evangelos Vassalos
Publikováno v:
Journal of Signal Processing Systems. 67:255-268
Architectures for designing single constant multipliers in Residue Number System (RNS) for moduli of the 2 n ?1, 2 n and 2 n ?+?1 forms are introduced with the constant operand being recoded in Signed-Digit representation. Two methodologies are propo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a5a582805742c01eb58c8ebe8c45da0f
https://doi.org/10.1007/s11265-010-0552-z
https://doi.org/10.1007/s11265-010-0552-z
Autor:
Haridimos T. Vergos, D. Bakalis
Publikováno v:
Journal of Circuits, Systems and Computers. 19:911-930
It is shown that a diminished-1 adder, with minor modifications, can be also used for the modulo 2n + 1 addition of two n-bit operands in the weighted representation, if the sum of its input operands is decreased by one. This modified diminished-1 ad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15a92ad8cb85d0861fc75d3564bdc604
https://doi.org/10.1142/s0218126610006529
https://doi.org/10.1142/s0218126610006529