Zobrazeno 1 - 6
of 6
pro vyhledávání: '"D. A. Zheleznikov"'
Publikováno v:
Russian Microelectronics. 50:509-515
The problem of analyzing and evaluating the structure of FPGA routing resources at early stages of the design flow presents great interest for researchers. Until now, an approach, consisting in passing the full design flow (logic synthesis, placement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6d0765ff83f10aebcc97b2f8a1194419
https://doi.org/10.1134/s1063739721070040
https://doi.org/10.1134/s1063739721070040
Autor:
V. I. Enns, S.V. Gavrilov, Mariya A. Zapletina, V.M. Khvatov, R. Zh. Chochaev, D. A. Zheleznikov
Publikováno v:
Russian Microelectronics. 48:176-186
A layout synthesis design flow for implementing designs on reconfigurable systems-on-chip is developed by the Institute for Design Problems in Microelectronics of Russian Academy of Sciences, in cooperation with JSC “NIIME” for special-purpose ci
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54fb987d0f7ff1655835f53ee696f23d
https://doi.org/10.1134/s1063739719030053
https://doi.org/10.1134/s1063739719030053
Autor:
D. A. Zheleznikov, V.M. Khvatov
Publikováno v:
2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus).
IP-core is a block with a complex function that can be re-used in integrated circuits design. There are two types of FPGA IP-cores: hard IP-core and soft IP-core. Hard IP-cores have an exact location and pre-routed interconnects while soft IP-cores c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bc767f09797bc728d7c00649f6e2f08c
https://doi.org/10.1109/elconrus51938.2021.9396219
https://doi.org/10.1109/elconrus51938.2021.9396219
Publikováno v:
2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus).
Soft programmable IP-cores are usually used to speed up the integrated circuits design in FPGA. Soft blocks are formed from programmable logical FPGA elements independently from specific location on the FPGA and do not have pre-routed paths. Some FPG
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::44d9b24835a7c9bd17441cf2a0a9d2d2
https://doi.org/10.1109/elconrus51938.2021.9396572
https://doi.org/10.1109/elconrus51938.2021.9396572
Publikováno v:
Russian Microelectronics. 47:516-521
The existing means of design automation are focused mainly on the technology of foreign manufacturers, which makes it necessary to adapt the existing methods and means for designing reconfigurable systems-on-a-chip and to develop domestic specialized
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0892e4c33bc4d52e8a48fd768c22ba31
https://doi.org/10.1134/s1063739718070028
https://doi.org/10.1134/s1063739718070028
Publikováno v:
2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus).
The well-known methods for evaluating the performance of digital circuits designed using the Field-Programmable Gate Array (FPGA) or Reconfigurable System on a Chip (RSoC) use simplified elements delay model or the simulation of the final post-routin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4c667a419249c9d783df9c71fb5b5345
https://doi.org/10.1109/eiconrus49466.2020.9039262
https://doi.org/10.1109/eiconrus49466.2020.9039262