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of 6
pro vyhledávání: '"Cyrille Dray"'
Autor:
Benoit Nadeau-Dostie, Lori Schramm, Jongsin Yun, Khushal Gelda, Cyrille Dray, Mehdi Boujamaa, Martin Keim
Publikováno v:
ITC
Access Memory) has many attractive properties such as small size, fast operation speed, and good endurance. However, MRAM has a relatively small TMR (Tunneling Magnetoresistance) ratio, which means a small on-off state separation. It is a challenge t
Autor:
Manuj Rathor, Suk-Soo Pyo, Steve Ngueya Wandji, Andrew Sowden, Jean Christophe Vial, Alexandra Gourio, Gwan-Hyeob Koh, El Mehdi Boujamaa, Jongwook Kye, Samsudeen Mohamed Ali, Yoon-Jong Song, Cyrille Dray, Taejoong Song
Publikováno v:
VLSI Circuits
In this paper we present a read circuitry that tackles all STT-MRAM read challenges. First, a negative temperature coefficient (NTC) reference based on an MTJ in series with an “NTC” resistor circuit emulator is described. Then, an offset cancell
Publikováno v:
ETS
eMRAM (embedded Magnetoresistive Random Access Memory) is an attractive solution in many non-volatile memory applications because of its small size, fast operation speed, and good endurance. However, due to a relatively small on/off resistance separa
Autor:
Alexandra Gourio, Surya Gupta, Akshay Kumar, Didier Gayraud, Laurent Vachez, Luc Palau, Piyush Jain, Jean-Christophe Buy, Abdelali El Amraoui, Giorgio Palma, Cyrille Dray, Nicolaas Van Winkelhoff
Publikováno v:
DATE
Spin Transfer Torque Magneto-resistive Random- Access Memory (STT-MRAM) is emerging as a promising substitute for flash memories due to scaling challenges for flash in process nodes beyond 28nm. STT-MRAM’s high endurance, fast speed and low power m
Publikováno v:
ISVLSI
The input-referred offset of a dynamic latch-based sense amplifier for resistive memories is extensively analyzed. This circuit is modeled using both small and large signal analysis, in order to evaluate mismatch effects and to support design robustn
Publikováno v:
2010 IEEE International Memory Workshop.
This paper describes an integrated SRAM standby power reduction design in a 40nm low power process. It features a closed-loop array leakage control with floating bitlines, reducing 46% of leakage current. It relies on self-refreshing virtual VDD cloc