Zobrazeno 1 - 10
of 129
pro vyhledávání: '"Cycle stealing"'
Publikováno v:
ACM Transactions on Modeling and Performance Evaluation of Computing Systems
ACM Transactions on Modeling and Performance Evaluation of Computing Systems, ACM, In press, pp.1-35
ACM Transactions on Modeling and Performance Evaluation of Computing Systems, 2021, 6 (2), pp.1-33. ⟨10.1145/3462774⟩
ACM Transactions on Modeling and Performance Evaluation of Computing Systems, ACM, In press, pp.1-35
ACM Transactions on Modeling and Performance Evaluation of Computing Systems, 2021, 6 (2), pp.1-33. ⟨10.1145/3462774⟩
Consider a setting where Willie generates a Poisson stream of jobs and routes them to a single server that follows the first-in first-out discipline. Suppose there is an adversary Alice, who desires to receive service without being detected. We ask t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c92918458f4f9b35cfc678574a87dcf3
https://hal.inria.fr/hal-03216762/document
https://hal.inria.fr/hal-03216762/document
Publikováno v:
Electronic Notes in Theoretical Computer Science. 318:5-17
Organisations such as research institutions and universities often increase utilisation of their office workstations by deploying a high-throughput cycle-stealing distributed system. Such systems allow users to submit a large number of computing task
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Publikováno v:
Microprocessors and Microsystems. 45:241-252
In a high-speed synthesis design environment, designers struggle to ensure that multi-clock and multi-power interfaces are designed, placed, connected and timed correctly. Identifying and applying proper timing constraints such as "no cycle stealing"
Publikováno v:
Electronic notes in theoretical computer science, 2015, Vol.310, pp.65-90 [Peer Reviewed Journal]
Checkpointing is a fault-tolerance mechanism commonly used in High Throughput Computing (HTC) environments to allow the execution of long-running computational tasks on compute resources subject to hardware or software failures as well as interruptio
Publikováno v:
2016 7th IEEE International Conference on Software Engineering and Service Science (ICSESS).
With the development of many-core processors, programmable intelligent engine many-core processor CPU allocation, and custom packet classification and load balancing transceiver offers the possibility, however, faced with a dozen or even hundreds of
Autor:
Vaibbhav Taraate
Publikováno v:
Digital Logic Design Using Verilog ISBN: 9788132227892
This chapter describes about the key sequential design guidelines used in the ASIC design. These guidelines are essential for any ASIC design and used to improve the readability, performance, and need to be followed by an ASIC design engineer. The ke
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::80e530215587c904f34b58213cff1ba5
https://doi.org/10.1007/978-81-322-2791-5_6
https://doi.org/10.1007/978-81-322-2791-5_6
Publikováno v:
Applied Mechanics and Materials. :1138-1141
The electric carrier communication is the special communicated way of electrical power system In this paper, one kind of double CPU, the low power loss, the low cost digital multiplexer has been designed in conducted the full research to this communi
Publikováno v:
Journal of Electronics (China). 29:128-131
This paper describes the method of built-in self-repairing of RAM on board, designs hardware circuit, and logic for the RAM’s faults self-repairing system based on FPGA. The key technology is that it utilizes FPGA to test RAM according to some algo
Publikováno v:
Journal of Grid Computing. 6:399-416
This paper presents a resource selection system for exploiting graphics processing units (GPUs) as general-purpose computational resources in desktop Grid environments. Our system allows Grid users to share remote GPUs, which are traditionally dedica