Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Curtis Tsai"'
Autor:
Inanc Meric, Chang Hsu-Yu, Olac-Vaw Roman W, M. Chahal, K. W. Park, C.-H. Jan, S. Novak, N. L. Dias, P. Bai, S. Ramey, Nidhi Nidhi, Curtis Tsai, Chetan Prasad, Hafez Walid M, Ramaswamy Rahul
Publikováno v:
2016 IEEE International Reliability Physics Symposium (IRPS).
The transistor reliability characterization of a 14nm System-on-Chip (SoC) node optimized for low power operation is described. In-depth assessments of reliability and performance for Core and I/O devices are performed on Logic and SoC nodes, and cle
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::239baa5f31ceaaa074c1c5b8511c55c9
https://doi.org/10.1109/irps.2016.7574536
https://doi.org/10.1109/irps.2016.7574536
Autor:
J. Lee, P. Bai, T. Leo, S. K.-Y. Shi, P. Vandervoorn, D. Ingerly, L. Rockford, Ramaswamy Rahul, Y.-W. Chen, Nidhi Nidhi, F. Al-Amoody, M. Jang, K. Byon, T. Rana, Curtis Tsai, A. Zainuddin, C. Quincy, Eric Karl, L. Yang, Hafez Walid M, Chetan Prasad, C. Petersburg, Olac-Vaw Roman W, K. Komeyli, A. Kumar, Chang Hsu-Yu, Anand Subramaniam, N. L. Dias, Tsung-Yuan Chang, H. Kilambi, K. Phoa, Pei-Chi Liu, Chen-Guan Lee, C.-H. Jan
Publikováno v:
VLSIC
A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3ad023e07edda7779db811903bcb46fb
https://doi.org/10.1109/vlsic.2015.7231380
https://doi.org/10.1109/vlsic.2015.7231380
Autor:
Bruce Woolery, Abdur Rahman, J.-Y. Yeh, P. Bai, M. Jamil, K. Phoa, C.-H. Jan, Curtis Tsai, G. Curello, J. Hicks, M. S. Rahman, Joodong Park
Publikováno v:
2013 IEEE International Reliability Physics Symposium (IRPS).
Transistor reliability characterization studies are reported for a state of the art 22nm 3-D tri-gate HK/MG SoC technology with logic and HV I/O transistor architecture. TDDB, BTI and HCI degradation modes for logic and I/O transistors are studied an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9fd0814444461441fe012d7275e86cfe
https://doi.org/10.1109/irps.2013.6532105
https://doi.org/10.1109/irps.2013.6532105
Autor:
Ian R. Post, Kaizad Mistry, P. Vandervoorn, Chetan Prasad, A. Schmitz, Paul A. Packan, Dhruv Singh, B. Niu, M. Agostinelli, Daniel Pantuso, P. Bai, S. Ramey, Sanjay Natarajan, Travis Eiles, J. Thomas, Sell Bernhard, J. Hicks, Lei Jiang, C. Auth, Chia-Hong Jan, S. Suthram, Curtis Tsai
Publikováno v:
2013 IEEE International Reliability Physics Symposium (IRPS).
This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bdf10a9b4063c91c8c77e92ca1ae6b46
https://doi.org/10.1109/irps.2013.6532036
https://doi.org/10.1109/irps.2013.6532036
Autor:
K. Komeyli, H. Tashiro, J.-Y. Yeh, Joodong Park, C. Staus, M. Kang, M. Jang, Uddalak Bhattacharya, P. Bai, Abdur Rahman, Chia-Hong Jan, Kinyip Phoa, Curtis Tsai, P. Vandervoorn, Ruth A. Brain, L. Yang, G. Curello, Nidhi Nidhi, S.-J. Choi, G. Gupta, Hafez Walid M, L. Pan, T. Leo
Publikováno v:
2012 International Electron Devices Meeting.
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::65cbc6de11013a48dd62c1a5522bbbc4
https://doi.org/10.1109/iedm.2012.6478969
https://doi.org/10.1109/iedm.2012.6478969
Autor:
Abdur Rahman, J.-Y. Yeh, M. Agostinelli, K. Phoa, G. Curello, P. Bai, Joodong Park, Curtis Tsai, Hafez Walid M, C.-H. Jan, K. Komeyli, H. Deshpande, J. Xu
Publikováno v:
2011 International Reliability Physics Symposium.
Extensive reliability characterization of a state of the art 32nm strained HK/MG SoC technology with triple transistor architecture is presented here. BTI, HCI and TDDB degradation modes on the Logic and I/O (1.2V, 1.8V and 3.3V tolerant) transistors
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ad3ffc66cc85e2e246a975e7733e28e
https://doi.org/10.1109/irps.2011.5784531
https://doi.org/10.1109/irps.2011.5784531
Autor:
Noboru Nakano, Rafael Reif, Curtis Tsai, Kenneth Liao, Julie Tsai, Hyoun-woo Kim, Syun‐Ming Jang, Louis Marville
Publikováno v:
Journal of Applied Physics. 73:414-417
The effect of thermal annealing on the Raman spectrum of Si1−xGex grown on Si was investigated in the temperature range of 800–1100 °C on three samples having Ge contents x of 0.2 and thicknesses of 0.08, 0.16, and 0.40 μm. For annealing below
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6074423710ee9c5463901104a0b781c
https://doi.org/10.1063/1.353864
https://doi.org/10.1063/1.353864
Autor:
S. Mudanai, Krishnamurthy Soumyanath, J. Lin, Abdur Rahman, Curtis Tsai, W.-K. Shin, Y-L Lu, Mohammed A El-Tanani, P. Bai, H. Tashiro, U. Jalan, Joodong Park, P. Vandervoorn, L. Janbay, M. Agostinelli, Hasnain Lakdawala, Chia-Hong Jan, Jad B. Rizk, M. Kang, Hafez Walid M, H. Deshpande, J.-Y. Yeh
Publikováno v:
2010 International Electron Devices Meeting.
The impact of silicon technology scaling trends and the associated technological innovations on RF CMOS device characteristics are examined. The application of novel strained silicon and high-k/metal gate technologies not only benefits digital system
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f8d7f897ac633830ba8e7f473b084cb5
https://doi.org/10.1109/iedm.2010.5703431
https://doi.org/10.1109/iedm.2010.5703431
Autor:
Mohammed A El-Tanani, H. Deshpande, Krishnamurthy Soumyanath, S. Mudanai, Abdur Rahman, Hafez Walid M, M. Agostinelli, Hasnain Lakdawala, U. Jalan, J.-Y. Yeh, L. Rockford, Stewart S. Taylor, Kwang-Jin Koh, P. Vandervoorn, L. Janbay, H. Tashiro, L. Yang, S.-J. Choi, M. Kang, P. Bai, Curtis Tsai, J. Lin, Jad B. Rizk, K. Phoa, Hongtao Xu, J. Xu, K. Komeyli, Nick Lindert, J. Yip, G. Sacks, Ian A. Young, C.-H. Jan, G. Curello, Joodong Park
Publikováno v:
2010 Symposium on VLSI Technology.
A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b6b5e40107c1a394af62bae286b1d46
https://doi.org/10.1109/vlsit.2010.5556201
https://doi.org/10.1109/vlsit.2010.5556201
Autor:
Ian R. Post, Hafez Walid M, Kaizad Mistry, K. Komeyli, Curtis Tsai, P. Bai, Chetan Prasad, J. Hicks, M. Jones, Roza Kotlyar, C.-H. Jan, J. Lin, S. Gannavaram
Publikováno v:
2010 IEEE International Reliability Physics Symposium.
In this paper, we present extensive reliability characterization results for a novel dual gate 45nm HK+MG technology. BTI, HCI and TDDB degradation modes on the Logic and I/O transistors are studied and excellent reliability is demonstrated. Emphasis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f391925a4e2a22a0aaddc59bef3388ee
https://doi.org/10.1109/irps.2010.5488815
https://doi.org/10.1109/irps.2010.5488815