Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Crockett Huang"'
Autor:
Yeh-Sheng Lin, Welch Lin, K. Liu, J. Y. Wu, Y. L. Hsieh, Hung-Chin Huang, P. Mukundhan, J. Tan, Crockett Huang, Chu-en Chen, R. P. Huang, J. Dai, C. W. Hsu, H. K. Hsu, W. C. Tsao, Chia Hung Lin, J. Chen
Publikováno v:
SPIE Proceedings.
High-K/metal gate technology, introduced by Intel, to replace the conventional oxide gate dielectric and polysilicon gate has truly revolutionized transistor technology more than any other change over the last 40 years. First introduced at the 45nm n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::423a5baeaae5e90e19cf85e538381e49
https://doi.org/10.1117/12.2011348
https://doi.org/10.1117/12.2011348
Autor:
Kung-Hsun Tsao, Hisashi Motobayashi, Katayama Tomohide, Crockett Huang, Yung-Cheng Chang, Chih-Jung Chen, Tsz-Yuan Chen, Simon Chiu, Nick Hsiao, Yu-Huan Liu, Vencent Chang, Go Noya
Publikováno v:
SPIE Proceedings.
Dual damascene technique has been widely applied to IC device fabrication in copper interconnect process. For traditional via-first dual damascene application, a fill material is first employed to fill via to protect over-etching and punch-through of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b96a60344d5a7a74ef31ccc65dfffdf
https://doi.org/10.1117/12.855997
https://doi.org/10.1117/12.855997
Publikováno v:
2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.
We proposed a novel method (DBB: Designed Based Binning) by using design and defect inspection information to detect marginal design features. This method was used to identify a pattern failure problem (hammer head) which occurred during production e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d986dca32ddcb3813fc12f1705effb7a
https://doi.org/10.1109/asmc.2008.4528996
https://doi.org/10.1109/asmc.2008.4528996
Publikováno v:
SPIE Proceedings.
As design rules continue to shrink beyond the lithography wavelength, pattern printability becomes a significant challenge in fabrication for 45nm and beyond. Model-based OPC and DRC checkers have been deployed using metrology data such as CD to fine
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1039cda9158e20172c09e2d9b0ef0405
https://doi.org/10.1117/12.772242
https://doi.org/10.1117/12.772242
Publikováno v:
SPIE Proceedings.
RRC (Reducing resist consumption) coating is widely used to reduce photo resist consumption. By using solvent to pre-wet the wafer surface, photo resist can be coated on wafer easier than normal coating method. But it also can be the source of defect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e800d0bfdf9d0fcb6041918a1d61799a
https://doi.org/10.1117/12.711933
https://doi.org/10.1117/12.711933