Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Craig W. MacNaughton"'
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXIII.
In an effort to keep scaling at the speed of Moore's law, novel methods are being developed to facilitate advanced semiconductor manufacturing at the 32nm node and beyond. One such method for enabling the creation of dense pitches beyond the current
Publikováno v:
SPIE Proceedings.
Overlay specifications are getting tighter and lithographic processes come close to their limits. Minimal process changes can lead occasionally to overlay excursions. We explore the use of advanced query and multivariate analysis techniques to addres
Autor:
William T. Knose, Stephen Hsu, Noel Corcoran, Michael Richie, Srinivas Vedula, J. Fung Chen, Douglas Van Den Broeke, Craig W. MacNaughton, Xuelong Shi
Publikováno v:
SPIE Proceedings.
Chromeless Phase Lithography (CPL) with a high NA exposure tool is shown to be an attractive technology solution for the 65nm node. Under strong image enhancement conditions, the traditional definition of minimum defect printability specifications is
Publikováno v:
SPIE Proceedings.
Optical proximity correction using both model-based and selective size adjust techniques was used as means to correct the distortion of patterns in silicon from drawn data. The performance of these corrections on silicon was evaluated using top-down
Autor:
John L. Sturtevant, Mike Pochkowski, John Miller, Craig W. MacNaughton, Frank Santos, Chris A. Mack, Moshe E. Preil, John A. Allgair, Michelle Ivy, Kevin D. Lucas, John C. Robinson, Richard C. Elliott
Publikováno v:
SPIE Proceedings.
One-dimensional linewidth alone is an inadequate metric for low-k1 lithography. Critical Dimension metrology and analysis have historically focused on 1-dimensional effects but with low-k1 lithography is has increasingly been found that the process w
Autor:
Herschel M. Marchman, Kevin M. Monahan, Jerry E. Schlesinger, Waiman Ng, Craig W. MacNaughton
Publikováno v:
SPIE Proceedings.
The 0.13 micrometer semiconductor manufacturing generation will have transistor gate structures as small as 100 nm, creating a demand for 10 nm gate linewidth control and for measurement precision on the order of 2 nm. This process control requiremen
Autor:
Rohit Malhotra, Richard C. Elliott, Waiman Ng, Mohan Ananth, Rich Quattrini, Craig W. MacNaughton, Jason C. Yee
Publikováno v:
SPIE Proceedings.
This paper presents results obtained using a low-voltage critical dimension scanning electron microscope (CD SEM) for the imaging and measurement of features patterned on quartz photomasks. The SEM system used was designed for handling silicon wafer