Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Craig S. Steele"'
Autor:
Craig S. Steele, J. P. Bonn
Publikováno v:
HPEC
Simulation of large computational systems-on-a-chip (SoCs) is increasing challenging as the number and complexity of components is scaled up. With the ubiquity of programmable components in computational SoCs, fast functional instruction-set simulati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9fc12d35fba95603bd0c0abaa0b38065
https://doi.org/10.1109/hpec.2012.6408664
https://doi.org/10.1109/hpec.2012.6408664
Publikováno v:
2006 49th IEEE International Midwest Symposium on Circuits and Systems.
This paper describes the architecture and implementation of an on-chip packet interface/router called the packet buffer (PBuf) employed in the MOrphable Networked microARCHitecture (MONARCH). This work provides a brief overview of MONARCH and its sub
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::779432d47a63abbc2cbc2770157ccfa1
https://doi.org/10.1109/mwscas.2006.381784
https://doi.org/10.1109/mwscas.2006.381784
Publikováno v:
ISCAS (3)
This paper describes the implementation of an area-efficient and protected user memory-mapped network interface, the pbuf (parcel buffer), for the data intensive architecture (DIVA) processing-in-memory (PIM) system. This implementation of the pbuf i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e2983ae4cde4e222f069e1d01e1c4d8e
https://doi.org/10.1109/iscas.2005.1465246
https://doi.org/10.1109/iscas.2005.1465246
Publikováno v:
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..
This paper describes the implementation of theexception handling mechanism in the second prototype version of the Data-Intensive Architecture (DIVA) processing-inmemory (PIM) chip. This implementation features architectural simplicity, low area (5428
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::47e098ef8440350d765c53ef1c2a4356
https://doi.org/10.1109/mwscas.2004.1354393
https://doi.org/10.1109/mwscas.2004.1354393
Publikováno v:
HPDC
The Packaging-Driven Scalable Systems multicomputer (PDSS) project uses several innovative interconnect and routing techniques to construct a low-latency, high-bandwidth (1.3 GB/s) multicomputer network. The PDSS network interface provides a low-late
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::46fb4dc87df2569268adf22101e58059
https://doi.org/10.1109/hpdc.1997.626407
https://doi.org/10.1109/hpdc.1997.626407
Autor:
Craig S. Steele, Mary Hall
Publikováno v:
Intelligent Memory Systems ISBN: 9783540423287
Intelligent Memory Systems
Intelligent Memory Systems
The DIVA (Data IntensiVe Architecture) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a host microprocessor. It exploits the inherently high on-chip memory bandwidth and additionally provides a separate memory-to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::42dcd0e186f2ea7128a7655212ac0de8
https://doi.org/10.1007/3-540-44570-6_7
https://doi.org/10.1007/3-540-44570-6_7
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540643593
IPPS/SPDP Workshops
IPPS/SPDP Workshops
ISI's Advanced Scalable Network Technology (ASNT) project employs multiple specialized network components in an integrated high-performance multicomputer system. Large multicomputer systems are vulnerable to programming error, hardware faults, and po
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c511381661b2fa9fe110e0fd11d74bf
https://doi.org/10.1007/3-540-64359-1_754
https://doi.org/10.1007/3-540-64359-1_754
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540643593
IPPS/SPDP Workshops
IPPS/SPDP Workshops
1. a exible thermal management system with the capability to remain viable for several generations of increased microprocessor performance and power, 2. simpli cation of the packaging, by eliminating the cooling core concept and replacing it with an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b32a405a9a1683afbc61b697d4c2273
https://doi.org/10.1007/3-540-64359-1_752
https://doi.org/10.1007/3-540-64359-1_752
Autor:
Craig S. Steele, Jacqueline Chame, Jeff LaCoss, Chun Chen, Jaewook Shin, Gokhan Daglikoca, Mary Hall, Ihn Kim, John J. Granacki, Chang Woo Kang, Jeffrey Draper, Tim Barrett
Publikováno v:
Scopus-Elsevier
ICS
ICS
The DIVA (Data IntensiVe Architecture) system incorporates a collection of Processing-In-Memory (PIM) chips as smart-memory co-processors to a conventional microprocessor. We have recently fabricated prototype DIVA PIMs. These chips represent the fir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::055d7d472ed673952653d0d2bd7a6c2d
http://www.scopus.com/inward/record.url?eid=2-s2.0-0036374270&partnerID=MN8TOARS
http://www.scopus.com/inward/record.url?eid=2-s2.0-0036374270&partnerID=MN8TOARS
Conference
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