Zobrazeno 1 - 10
of 34
pro vyhledávání: '"Craig Riddet"'
Autor:
Asen Asenov, Andrew R. Brown, Xingsheng Wang, Craig Riddet, Louis Gerrer, Vihar P. Georgiev, Ewan Towie, Salvatore Maria Amoroso
Publikováno v:
IEEE Transactions on Electron Devices. 61:4014-4018
In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scal
Autor:
Craig Riddet, Binjie Cheng, Greg Yeric, Xingsheng Wang, Asen Asenov, Saurahb Sinha, Robert Campbell Aitken, Salvatore Maria Amoroso, Lucian Shifren, Fikru Adamu-Lema
Publikováno v:
IEEE Transactions on Electron Devices. 61:3372-3378
In this paper, by means of simulation, we have studied the implications of using channel doping to control the threshold voltage and the leakage current in bulk silicon FinFETs suitable for the 10-nm CMOS technology generation. The channel doping lev
Autor:
Andrew R. Brown, Craig Riddet, Saurabh Sinha, Binjie Cheng, Robert Campbell Aitken, Brian Cline, Craig Alexander, Lucian Shifren, Greg Yeric, Asen Asenov, Vikas Chandra, Campbell Millar
Publikováno v:
IEEE Transactions on Electron Devices. 61:2271-2277
In this paper, we study and compare Si versus Ge pMOS FinFETs at advanced node dimensions using ensemble Monte Carlo simulations. It is found that due to large external resistance, lack of stressing methods, smaller bandgap, larger dielectric constan
Autor:
Craig Riddet, K. H. Chan, Evan H. C. Parker, Terry E. Whall, David R. Leadley, Asen Asenov, Jeremy R. Watling
Publikováno v:
IEEE Transactions on Electron Devices. 59:1878-1884
We present a comprehensive study of hole transport in germanium layers on “virtual” substrates using a full band Monte Carlo simulation approach, considering alternate “virtual” substrate and channel orientations and including the impact of t
Autor:
Robert Campbell Aitken, Y. Wang, Lucian Shifren, Andrew R. Brown, Salvatore Maria Amoroso, Greg Yeric, Xingsheng Wang, Ewan Towie, Craig Riddet, Jinfeng Kang, Talib Al-Ameri, Xiaoyan Liu, Asen Asenov, Binjie Cheng, Saurabh Sinha, Vihar P. Georgiev, David Reid
In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8121893761e03623c9fb488581f5b17c
https://eprints.gla.ac.uk/110788/2/110788.pdf
https://eprints.gla.ac.uk/110788/2/110788.pdf
Publikováno v:
Microelectronic Engineering. 88:362-365
In this paper a drift diffusion simulation study of a 20nm gate-length implant-free quantum well germanium p-MOSFET is presented, which covers the impact of mobility, velocity saturation and density of interface states on the transistor performance.
Publikováno v:
IEEE Transactions on Electron Devices. 58:600-608
In this paper, we report a 3-D Monte Carlo (MC) simulation methodology that includes complex quantum confinement effects captured through the introduction of robust and efficient density gradient (DG) quantum corrections (QCs), which has been used to
Publikováno v:
IEEE Transactions on Electron Devices. 57:2418-2426
Quantum corrections based on density gradient formalism, recently introduced in the 3-D Monte Carlo (MC) module of the Glasgow “atomistic” simulator, are used to simultaneously capture quantum confinement effects as well as “ab initio” ionize
Publikováno v:
Journal of Computational Electronics. 7:231-235
Monte Carlo remains an effective simulations methodology for the study of MOSFET devices well into the decananometre regime as it captures non-equilibrium and quasi-ballistic transport. The inclusion of quantum corrections further extends the usefuln
Publikováno v:
IEEE Transactions On Nanotechnology. 6:48-55
For the scaling of ultrathin body double gate (UTB DG) MOSFETs to channel lengths below 10 nm, a silicon body thickness of less than 5 nm is required. At these dimensions the influence of atomic scale roughness at the interface between the silicon bo